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| FDC37C93xAPM ADVANCE INFORMATION Plug and Play Compatible Ultra I/OTM Controller with Soft Power Management FEATURES * * * * 5 Volt Operation ISA Plug-and-Play Standard (Version 1.0a) Compatible Register Set Soft Power Management, SMI Support ACPI/Legacy Support - SCI/SMI Support - Power Management Timer - Power Button Override Event - Either Edge Triggered Interrupts ACCESS.bus Support 8042 Keyboard Controller - 2K Program ROM - 256 Bytes Data RAM - Asynchronous Access to Two Data Registers and One Status Register - Supports Interrupt and Polling Access - 8 Bit Timer/Counter - Port 92 Support - Fast Gate A20 and Hardware Keyboard Reset Real Time Clock - MC146818 and DS1287 Compatible - 256 Bytes of Battery Backed CMOS in Two Banks of 128 Bytes - 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks - 12 and 24 Hour Time Format - Binary and BCD Format - 1 A Standby Current (typ) Intelligent Auto Power Management 2.88MB Super I/O Floppy Disk Controller - Relocatable to 480 Different Addresses - 13 IRQ Options Four DMA Options Licensed CMOS 765B Floppy Disk Controller - Advanced Digital Data Separator - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - Game Port Select Logic - Supports Two Floppy Drives Directly - 24mA AT Bus Drivers - Low Power CMOS Design Licensed CMOS 765B Floppy Disk Controller Core - Supports Vertical Recording Format - 16 Byte Data FIFO - 100% IBM(R) Compatibility - Detects All Overrun and Underrun Conditions - 48mA Drivers and Schmitt Trigger Inputs - DMA Enable Logic - Data Rate and Drive Control Registers Enhanced Digital Data Separator - Low Cost Implementation - No Filter Components Required - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Serial Ports - Relocatable to 480 Different Addresses - * * * * * * * * TABLE OF CONTENTS FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION..................................................................................................................4 PIN CONFIGURATION.......................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS...........................................................................................6 FUNCTIONAL DESCRIPTION ..........................................................................................................15 SUPER I/O REGISTERS ...........................................................................................................15 HOST PROCESSOR INTERFACE.............................................................................................15 FLOPPY DISK CONTROLLER...................................................................................................16 FDC INTERNAL REGISTERS....................................................................................................16 INSTRUCTION SET .........................................................................................................................44 SERIAL PORT (UART) .....................................................................................................................70 INFRARED INTERFACE...................................................................................................................85 PARALLEL PORT.............................................................................................................................86 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES..............................................88 EXTENDED CAPABILITIES PARALLEL PORT ..........................................................................95 AUTO POWER MANAGEMENT .....................................................................................................111 INTEGRATED DRIVE ELECTRONICS INTERFACE .......................................................................116 HOST FILE REGISTERS .........................................................................................................116 TASK FILE REGISTERS..........................................................................................................116 IDE OUTPUT ENABLES ..........................................................................................................117 BIOS BUFFER.........................................................................................................................118 GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION ...............................................................121 EITHER EDGE TRIGGERED INTERRUPTS ............................................................................135 8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL DESCRIPTION ...........136 SOFT POWER MANAGEMENT......................................................................................................161 SYSTEM MANAGEMENT INTERRUPT (SMI) .................................................................................165 ACCESS.BUS ................................................................................................................................166 ACPI FEATURES ...........................................................................................................................172 CONFIGURATION...................................................................................................................188 OPERATIONAL DESCRIPTION......................................................................................................238 POWER SUPPLY OPERATIONAL MODES .............................................................................242 TIMING DIAGRAMS ................................................................................................................243 ECP PARALLEL PORT TIMING......................................................................................................270 80 Arkay Drive Hauppauge, NY. 11788 (516) 435-6000 FAX (516) 273-3123 2 * * * 13 IRQ Options Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Programmable Baud Rate Generator - Modem Control Circuitry Including 230K and 460K Baud - IrDA, HP-SIR, ASK-IR Support IDE Interface - Relocatable to 480 Different Addresses - 13 IRQ Options (IRQ Steering through Chip) - Two Channel/Four Drive Support - On-Chip Decode and Select Logic Compatible with IBM PC/XT(R) and PC/AT(R) Embedded Hard Disk Drives Serial EEPROM Interface Multi-ModeTM Parallel Port with ChiProtectTM - Relocatable to 480 Different Addresses - 13 IRQ Options - * * * Four DMA Options Standard Mode - IBM PC/XT, PC/AT, and PS/2TM Compatible Bidirectional ParallelPort - Enhanced Mode - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - High Speed Mode - Microsoft and Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtectTM Circuitry for Protection Against Damage Due to Printer Power-On - 12 mA Output Drivers ISA Host Interface 16 Bit Address Qualification 160 Pin QFP Package - *Note: The "X" in the Ultra I/O part number is a designator that changes depending upon the particular BIOS used inside the specific chip. "2" denotes AMI Keyboard BIOS/"5" denotes Phoenix Keyboard BIOS. 3 GENERAL DESCRIPTION The FDC37C93xAPM incorporates a keyboard interface, real-time clock, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, IDE interface, on-chip 24 mA AT bus drivers, game port chip select and two floppy direct drive support, as well as ACCESS.bus, soft power management and SMI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both onchip UARTs are compatible with the NS16C550. The parallel port, the IDE interface, and the game port select logic are compatible with IBM PC/AT architecture, as well as EPP and ECP. The FDC37C93xAPM incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37C93xAPM provides features for compliance with the "Advanced Configuration and Power Interface Specification" (ACPI). These features include support of both legacy and ACPI power management models through the selection of SMI or SCI. It implements a 24bit power management timer, power button override event (4 second button hold to turn off the system) and either edge triggered interrupts. The FDC37C93xAPM provides support for the ISA Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows '95. Through internal configuration registers, each of the FDC37C93xAPM's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 13 IRQ options, and three DMA channel options for each logical device. The FDC37C93xAPM does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. The FDC37C93xAPM is software and register compatible with SMSC's proprietary 82077AA core. IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation 4 PIN CONFIGURATION nDTR2 nCTS2 nRTS2 nDSR2 TXD2 RXD2 nDCD2 nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTB nALF nERROR nINIT nSLCTIN VCC PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND nACK BUSY PE SLCT VCC XTAL2 GND XTAL1 VBAT GND DRVDEN0 DRVDEN1 nMTR0 nDS1 nDS0 nMTR1 GND nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG MEDIA_ID1 mEDIA_ID0 VCC CLOCKI nIDE1_OE nHDCS0 nHDCS1 IDE1_IRQ nHDCS2/SA13 nHDCS3/SA14 IDE2_IRQ/SA15 nIOROP nIOWOP VTR nPOWER ON BUTTON_IN HCLK 16CLK CLK01 CLK02 CLK03 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 FDC37C93xAPM 160 Pin QFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nROMDIR nROMCS RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 GP25 GP24 GP23 GP22 GP21 GP20 GP17 GP16 GP15 VCC GP14 GP13 GP12 GP11 GP10 GND MCLK MDAT KCLK KDAT IOCHRDY TC DRQ3 nDACK3 DRQ2 nDACK2 DRQ1 nDACK1 DRQ0 nDACK0 5 RESET_DRV SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 nCS/SA12 IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 VCC IRQ8/nIRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1 nIOR nIOW AEN GND SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DESCRIPTION OF PIN FUNCTIONS PIN NO. 72:79 41:52 53 70 90 80 67:61, 59:54 82,84, 86,88 81,83, 85,87 89 68 69 35 36 22 37 38 39 21, 60, 101, 125, 139 32 1, 8, 40, 71, 95, 123, 130 17 System Data Bus System Address Bus Chip Select/SA12 (Active Low)(Note 1, 4) Address Enable (DMA master has bus control) I/O Channel Ready Reset Drive Interrupt Requests [1,3:12,14,15] (Polarity control for IRQ8) DMA Requests DMA Acknowledge Terminal Count I/O Read I/O Write High Speed Clock Out 24/48 MHz 16 MHz Out 14.318 MHz Clock Input 14.318 MHz Clock Output 1 14.318 MHz Clock Output 2 14.318 MHz Clock Output 3 POWER PINS +5V Supply Voltage VCC NAME PROCESSOR/HOST INTERFACE SD[0:7] SA[0:11] nCS AEN IOCHRDY RESET_DRV IRQ[1,3:12, 14,15] DRQ[0:3] nDACK[0:3] TC nIOR nIOW HCLK 16CLK CLOCKI CLKO1 CLKO2 CLKO3 I/O24 I I I OD24 IS 024/OD24 (Note 0) O24 I I I I O20 O8SR ICLK O16SR O8SR O8SR SYMBOL BUFFER TYPE Trickle Voltage Input Ground VTR GND FDD INTERFACE Read Disk Data nRDATA IS 6 DESCRIPTION OF PIN FUNCTIONS PIN NO. 12 11 13 9 10 18 5,6 7,4 16 15 14 3,2 19,20 Write Gate Write Disk Data Head Select (1 = side 0) Step Direction (1 = out) Step Pulse Disk Change Drive Select Lines Motor On Lines Write Protected Track 0 Index Pulse Input Drive Density Select [1:0] Media ID inputs. In floppy enhanced mode 2 these inputs are the media ID [1:0] inputs. (Note 4) SERIAL PORT 1 INTERFACE 145 146 148 149 150 147 152 151 155 156 158 159 160 157 Receive Serial Data 1 Transmit Serial Data 1 Request to Send 1 Clear to Send 1 Data Terminal Ready 1 Data Set Ready 1 Data Carrier Detect 1 Ring Indicator 1 SERIAL PORT 2 INTERFACE Receive Serial Data 2 (Note 4) Transmit Serial Data 2 (Note 4) Request to Send 2 (Note 4) Clear to Send 2 (Note 4) Data Terminal Ready 2 (Note 4) Data Set Ready 2 (Note 4) RXD2 TXD2 nRTS2 nCTS2 nDTR2 nDSR2 I O4 O4 I O4 I RXD1 TXD1 nRTS1 nCTS1 nDTR1 nDSR1 nDCD1 nRI1 I O4 O4 I O4 I I I NAME SYMBOL nWGATE nWDATA nHDSEL nDIR nSTEP nDSKCHG nDS[1:0] nMTR[1:0] nWPROT nTR0 nINDEX DRVDEN [1:0] MID[1:0] BUFFER TYPE OD48 OD48 OD48 OD48 OD48 IS OD48 OD48 IS IS IS OD48 IS 7 DESCRIPTION OF PIN FUNCTIONS PIN NO. 154 153 23 24 25 30 31 26 27 28 29 138:131 140 141 143 144 128 129 127 126 142 122 124 121 91 NAME Data Carrier Detect 2 (Note 4) Ring Indicator 2 (Note 4) IDE1 INTERFACE IDE1 Enable (Note 4) IDE1 Chip Select 0 (Note 4) IDE1 Chip Select 1 (Note 4) IOR Output (Note 4) IOW Output (Note 4) IDE1 Interrupt Request (Note 4) IDE2 INTERFACE IDE2 Chip Select 2/SA13 (Note 3, 4) IDE2 Chip Select 3/SA14 (Note 3, 4) IDE2 Interrupt Request/SA15 (Note 4) PARALLEL PORT INTERFACE Parallel Port Data Bus Printer Select Initiate Output Auto Line Feed Strobe Signal Busy Signal Acknowledge Handshake Paper End Printer Selected Error at Printer REAL-TIME CLOCK 32 Khz Crystal Input 32 Khz Crystal Output Battery Voltage KEYBOARD/MOUSE Keyboard Data KDAT I/OD16P XTAL1 XTAL2 Vbat ICLK2 OCLK2 PD[0:7] nSLCTIN nINIT nALF nSTB BUSY nACK PE SLCT nERROR I/O24 OD24/O24 OD24/O24 OD24/O24 OD24/O24 I I I I I nHDCS2 nHDCS3 IDE2_IRQ I/O24 I/O24 I nIDE1_OE nHDCS0 nHDCS1 nIOROP nIOWOP IDE1_IRQ O4 O24 O24 O24 O24 I SYMBOL nDCD2 nRI2 BUFFER TYPE I I 8 DESCRIPTION OF PIN FUNCTIONS PIN NO. 92 93 94 33 34 96 97 98 99 100 102 103 104 105 106 107 108 109 110 111:118 119 120 Note 0: Keyboard Clock Mouse Data Mouse Clock Power On (Note 4) Button Input (Note 4) GENERAL PURPOSE I/O GPI/O; IRQ In (Note 4) GPI/O; IRQ In/IRQ 13 (Note 4) GPI/O; WD Timer Output/IRRX (Note 4) GPI/O; Power Led Output/IRTX (Note 4) GPI/O; GP Address Decode (Note 4) GPI/O; GP Write Strobe (Note 4) GPI/O; Joy Read Strobe/JOYCS (Note 4) GPI/O; Joy Write Strobe (Note 4) GPI/O; IDE2 Output Enable/8042 P20 (Note 4) GPI/O; Serial EEPROM Data In/AB_DATA (Note 4) GPI/O; Serial EEPROM Data Out/AB_CLK (Note 4) GPI/O; Serial EEPROM Clock (Note 4) GPI/O; Serial EEPROM Enable (Note 4) GPI/O; 8042 P21 (Note 4) BIOS BUFFERS ROM Bus (I/O to the SD Bus) (Note 4) ROM Chip Select (only used for ROM) (Note 4) RD[0:7] nROMCS I/O4 I I GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 I/O4 I/O4 I/O4 I/O24 I/O4 I/O4 I/O4 I/O4 I/O4 I/O8 I/O8 I/O4 I/O4 I/O4 NAME SYMBOL KCLK MDAT MCLK nPowerOn Button_In SOFT POWER MANAGEMENT INTERFACE I/O24 I/O24 BUFFER TYPE I/OD16P I/OD16P I/OD16P ROM Output Enable (DIR) (only used for ROM) (Note 4) nROMDIR Note 1: The interrupt request is output on one of the IRQx signals as 024 buffer type. If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. In this case, the buffer type is OD24. Refer to the configuration section for more information. nCS -This pin is the active low chip select; it must be low for all chip accesses. For 12 bit addressing, SA0:SA11, this input should be tied to GND. For 16 bit address qualification, 9 Note 2: Note 3: Note 4: address bits SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15. nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal nHDCS2 and nHDCS3 require a pull-up to ensure a logic high at power-up when used for IDE2 until the Active Bit is set to 1. See Table on the following page for Multifunction Pins with GPI/O and Other Alternate Functions. 10 Description of Multifunction Pins with GPI/O and Other Alternate Functions Pin No. 19 20 23 24 25 26 30 31 33 Original Function MEDIA_ID1 MEDIA_ID0 nIDE1_OE nHDCS0 nHDCS1 IDE1_IRQ nIOROP nIOWOP nPowerOn Alternate Function 1 GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O Alternate Function 2 Power LED Output nSMI Alternate Function 3 WDT Buffer Type I/O8 I/O8 I/O4 I/O24 I/O24 I/O8 I/O24 I/O24 I/O24 Default float float high high high float float float active low open collector output input RD0 RD0 RD0 RD0 RD0 RD0 RD0 RD0 1,4 Index Register GP4 GP4 GP4 GP4 GP4 GP4 GP4 GP4 GP5 GPI/O GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP51 34 111 112 113 114 115 116 117 118 119 120 153 154 155 156 157 158 159 160 Button_In RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 nROMCS nROMOE nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O Power LED Output WDT 8042 - P12 8042 - P13 8042 - P14 8042 - P15 8042 - P16 8042 - P17 - - I/O24 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 GP5 GP6 GP6 GP6 GP6 GP6 GP6 GP6 GP6 GP50 GP60 GP61 GP62 GP63 GP64 GP65 GP66 GP67 GP53 GP54 GP70 GP71 GP72 GP73 GP74 GP75 GP76 GP77 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1 1 nROMCS nROMCS 2 2 2 2,4 GP5 GP5 GP7 GP7 GP7 GP7 GP7 GP7 GP7 GP7 input input input input input, input input input 2 2,4 (2) 2,4 11 Pin No. 27 28 29 53 96 97 98 Original Function nHDCS2 nHDCS3 IDE2_IRQ nCS/SA 12 GPI/O GPI/O GPI/O Alternate Function 1 SA13 SA14 SA15 IRQ in IRQ in WDT Timer Output/ IRRX Power LED Output/ IRTX GP Address Decode GP Write Strobe Joy Read Strobe Joy Write Strobe IDE2 Output Enable Serial EEPROM Data In Serial EEPROM Data Out Serial EEPROM Clock Serial EEPROM Enable 8042 P21 Alternate Function 2 IRQ13 - Alternate Function 3 - Buffer Type I/O24 I/O24 I I I/O4 I/O4 I/O4 Default float float float input input input input Index Register GP1 GP1 GP1 GPI/O GP10 GP11 GP12 99 100 102 103 104 105 106 GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O GPI/O JOYCS 8042 P20 AB_DATA - I/O24 I/O4 I/O4 I/O4 I/O4 I/O4 I/O8 /OD8 (EN1) I/O8 /OD8 (EN1) I/O4 I/O4 I/O4 input input input input input input input GP1 GP1 GP1 GP1 GP1 GP2 GP2 GP13 GP14 GP15 GP16 GP17 GP20 GP21 107 GPI/O AB_CLK - input GP2 GP22 108 109 110 GPI/O GPI/O GPI/O - - input input input GP2 GP2 GP2 GP23 GP24 GP25 Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0-RD7 for functions other than the XD Bus, nROMCS must stay high until those pins are finished being reprogrammed. Note 2: These pins are input (high-z) until programmed for second serial port. Note 3: This is the trickle voltage input pin for the FDC37C93xAPM. Note 4: These pins cannot be programmed as open drain pins in their original function. Note: No pins in their original function can be programmed as inverted input or inverted output. 12 BUFFER TYPE DESCRIPTIONS BUFFER TYPE I IS I/OD16P I/O24 I/O4 O4 O8SR O16SR O20 O24 OD24 OD48 ICLK ICLK2 OCLK2 DESCRIPTION Input, TTL compatible. Input with Schmitt trigger. Input/Output, 16mA sink, 90uA pull-up. Input/Output, 24mA sink, 12mA source. Input/Output, 4mA sink, 2mA source. Output, 4mA sink, 2mA source. Output, 8mA sink, 4mA source with Slew Rate Limiting. Output, 16mA sink, 8mA source with Slew Rate Limiting. Output, 20mA sink, 10mA source. Output, 24mA sink, 12mA source. Output, Open Drain, 24mA sink. Output, Open Drain, 48mA sink. Clock Input Clock Input Clock Output 13 nSMI* IRQ13* nPowerOn Button_In VTR SOFT POWER MANAGEMENT nGPA nGPCS* nGPWR* POWER MANAGEMENT BIOS BUFFER SMI ACPI/SCI nROMDIR nROMCS RD[0:7] PD0-7 MULTI-MODE PARALLEL PORT/FDC MUX BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF DECODER DATA BUS AB_DATA* AB_CLK* DATAIN* DATAOUT* CLK*, ENABLE* CONFIGURATION REGISTERS nIOR nIOW CONTROL BUS AEN SERIAL EEPROM ACCESS.bus ADDRESS BUS GENERAL PURPOSE I/O GP1[0:7]* GP2[0:5]* GP[4[0:7]*, GP5[0:1,3:4]*, GP6[0:7]*, GP7[0:7]* TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI1, nDTR1 16C550 COMPATIBLE SERIAL PORT 1 IRRX*, IRTX* SA[0:12] (nCS) SA[13-15] SD[O:7] DRQ[0:3] nDACK[0:3] TC IRQ[1,3-12,14,15] RESET_DRV IOCHRDY nINDEX DENSEL nDS0,1 nTRK0 nMTR0,1 nDIR nWDATA nRDATA nDSKCHG nSTEP DRVDEN0 nWRPRT nHDSEL DRVDEN1 ICLOCK nWGATE (14.318) MID0, MID1 HCLK CLKO[1:3] (14.318) 16CLK *Multi-Function I/O Pin - Optional CLOCK GEN 8042 WDATA WCLOCK SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE RCLOCK RDATA DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED TXD2(IRTX), nCTS2, nRTS2 RXD2(IRRX) nDSR2, nDCD2, nRI2, nDTR2 nHDCS2,3 IDE2_IRQ IDE1_IRQ IDE INTERFACE nIDE1_OE nIOWOP nIOROP nHDCS0, nHDCS1 KCLK KDATA MCLK MDATA P20*, P21* P12*, P13*, P14*,P15*, P16*, P17* XTAL1,2 VBAT HOST CPU INTERFACE IDE2 OPTIONAL RTC Vcc Vss FDC37C93xAPM BLOCK DIAGRAM 14 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports, Bank 2 of the RTC registers, auxiliary I/O and ACCESS.bus can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE The host processor communicates with the FDC37C93xAPM through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide except the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. Table 1 - Super I/O Block Addresses LOGICAL ADDRESS BLOCK NAME DEVICE Base+(0-5) and +(7) Base+(0-7) Base+(0-7) Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base1+(0-7), Base2+(0) Base1+(0-7), Base2+(0) 70, 71 Base2+(0,1) 60, 64 Base1+(0) Base2+(0) Base+(0-3) Base1+(0-11) Base2+(0-7) Floppy Disk Serial Port Com 1 Serial Port Com 2 Parallel Port SPP EPP ECP ECP+EPP+SPP IDE 1 IDE 2 RTC KYBD Aux. I/O ACCESS.bus ACPI 0 4 5 3 NOTES IR Support 1 2 6 7 8 9 A GPR GPW Note: Refer to the configuration register descriptions for setting the base address 15 FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 Table 2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) SECONDARY ADDRESS R/W REGISTER 370 R Status Register A (SRA) 371 R Status Register B (SRB) 372 R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TSR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) 16 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk PS/2 Mode 7 INT PENDING 0 6 nDRV2 N/A 5 STEP 0 interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0-D7 are held in a high impedance state for a read of address 3F0. 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 RESET COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 17 PS/2 Model 30 Mode 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 3 TRK0 nHDSEL N/A 1 2 INDX N/A 1 WP N/A 0 nDIR 1 RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 18 STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and PS/2 Mode 7 1 RESET COND. 1 6 1 1 Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". 19 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. 20 DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. RESET COND. 3 2 1 0 DMAEN nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 0 BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the four drive selects DS0 -DS3, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. When this bit is a a logic "0" it disables the nDACK and TC inputs and holds the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 7 MOTOR ENABLE 3 This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active. Table 3 - Drive Activation Values DRIVE 0 1 2 3 DOR VALUE 1CH 2DH 4EH 8FH 21 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC does not require its characteristics modified for tape support. The contents of this register are not used internal to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode. Table 4 - Tape Select Bits DRIVE SELECTED None 1 2 3 TAPE SEL1 0 0 1 1 TAPE SEL2 0 1 0 1 Table 5 - Internal 2 Drive Decode - Normal DRIVE SELECT MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER OUTPUTS (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 1 0 1 1 1 0 1 1 1 1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X 0 0 0 1 1 X 0 1 0 1 X 0 1 1 1 1 1 0 1 1 1 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 4 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 5 22 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 REG 3F3 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 REG 3F3 Media ID1 DB6 Media ID0 DB5 DB4 DB3 DB2 DB1 tape sel1 DB0 tape sel0 Drive Type ID Floppy Boot Drive For this mode, MEDIA_ID[1:0] pins are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by a hard or soft reset. BIT 7 MEDIA ID 1 READ ONLY (Pin 19) (See Table 7) BIT 6 MEDIA ID 0 READ ONLY (Pin 20) (See Table 8) BIT 5 and 4 reflect two of two bits these selected in the (See Table 9) DRIVE TYPE ID - These bits the bits of L0-CRF1. Which are depends on the last drive Digital Output Register (3F2). Note: L0-CRF1-B5 = Logical Device Configuration Register F1, Bit 5 0, BIT 3 and 2 FLOPPY BOOT DRIVE - These bits reflect the value of L0-CRF1. Bit 3 = L0CRF1-B7. Bit 2 = L0-CRF1-B6. BIT 1 AND 0 - TAPE DRIVE SELECT (READ/WRITE). Same as in Normal and Enhanced Floppy Mode. 1. Table 7 - Media ID1 MEDIA ID1 INPUT Pin 19 0 1 BIT 7 L0-CRF1-B5 =0 0 1 L0-CRF1-B5 =1 1 0 INPUT Pin 20 0 1 Table 8 - Media ID0 MEDIA ID0 BIT 6 CRF1-B4 =0 0 1 CRF1-B4 =1 1 0 23 Table 9 - Drive Type ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 0 0 1 1 Bit 0 0 1 0 1 Bit 5 L0-CRF2 - B1 L0-CRF2 - B3 L0-CRF2 - B5 L0-CRF2 - B7 Bit 4 L0-CRF2 - B0 L0-CRF2 - B2 L0-CRF2 - B4 L0-CRF2 - B6 Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. 24 DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 7 6 S/W POWER RESET DOWN 0 0 5 0 0 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. RESET COND. 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PRE- DRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 - 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 10 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Table 10 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec) <2Mbps 0.00 41.67 83.34 125.00 166.67 208.33 250.00 Default 2Mbps* 0 20.8 41.7 62.5 83.3 104.2 125 Default Default: See Table 12 *2Mbps data rate is only available if VCC = 5V. 25 DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 Table 11 - Data Rates DATA RATE DATA RATE DENSEL SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins. Table 12 - DRVDEN Mapping DRVDEN1 (1) DRVDEN0 (1) DRATE0 DENSEL DT1 0 DT0 0 DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2 1 0 1 0 1 1 DRATE0 DRATE0 DRATE1 DRATE1 nDENSEL DRATE0 26 Table 13 - Default Precompensation Delays DATA RATE 2 Mbps* 1 Mbps 500 Kbps 300 Kbps 250 Kbps PRECOMPENSATION DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns *The 2Mbps data rate is only available if VCC = 5V. 27 MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be 7 RQM 6 DIO 5 NON DMA 4 CMD BUSY read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer. 3 DRV3 BUSY 2 DRV2 BUSY 1 DRV1 BUSY 0 DRV0 BUSY BIT 0-3 DRVx BUSY These bits are set to "1"s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a "1" when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a "0" after the last command byte. BIT 5 NON-DMA This mode is selected in the SPECIFY command and will be set to a "1" during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A "1" indicates a read and a "0" indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a "1". No access is permitted if set to a "0". 28 DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 14 gives several examples of the delays with a FIFO. The data is based upon the following formula: Threshold # x 1 DATA RATE x8 - 1.5 s = DELAY At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 14 - FIFO Service Delay FIFO THRESHOLD MAXIMUM DELAY TO SERVICING EXAMPLES AT 2 Mbps* DATA RATE 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s *The 2 Mbps data rate is only available if VCC = 5V. 29 DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC/AT Mode 7 DSK CHG N/A 6 5 4 3 2 1 0 RESET COND. N/A N/A N/A N/A N/A N/A N/A BIT 0 - 6 UNDEFINED The data bus outputs D0-6 will remain in a high impedance state during a read of this register. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 1 0 DRATE DRATE nHIGH SEL1 SEL0 nDENS N/A N/A 1 RESET COND. BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BIT 1 and 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware reset. BIT 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. 30 Model 30 Mode 7 DSK CHG N/A 6 0 0 5 0 0 4 0 0 3 2 1 0 DMAEN NOPREC DRATE DRATE SEL1 SEL0 0 0 1 0 RESET COND. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BIT 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the pin. 31 CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 5 4 3 2 1 0 DRATE DRATE SEL1 SEL0 1 0 RESET COND. N/A N/A N/A N/A N/A N/A BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values. PS/2 Model 30 Mode 7 6 5 4 BIT 2 - 7 RESERVED Should be set to a logical "0" 3 RESET COND. N/A N/A N/A N/A N/A 2 1 0 NOPREC DRATE DRATE SEL1 SEL0 N/A 1 0 BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 12 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. 32 STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 15 - Status Register 0 NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". H DS1,0 Head Address Drive Select The current head address. The current selected drive. BIT NO. 7,6 SYMBOL IC 5 SE Seek End 4 EC Equipment Check 3 2 1,0 33 BIT NO. 7 SYMBOL EN Table 16 - Status Register 1 NAME DESCRIPTION End of Cylinder The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. 6 5 4 DE OR Data Error Overrun/ Underrun 3 2 ND No Data 1 NW Not Writable 0 MA Missing Any one of the following: Address Mark 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. 34 BIT NO. 7 6 SYMBOL CM Table 17 - Status Register 2 NAME DESCRIPTION Unused. This bit is always "0". Control Mark Any one of the following: 1. Read Data command - the FDC encountered a deleted data address mark. 2. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". 5 4 3 2 1 DD WC Data Error in Data Field Wrong Cylinder BC Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. 0 MD Missing Data The FDC cannot detect a data address mark or a Address Mark deleted data address mark. 35 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP Table 18- Status Register 3 NAME DESCRIPTION Unused. This bit is always "0". Write Protected Track 0 Head Address Drive Select Indicates the status of the WP pin. Unused. This bit is always "1". T0 HD DS1,0 Indicates the status of the TRK0 pin. Unused. This bit is always "1". Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins. RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the powerdown state. All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. RESET Pin (Hardware Reset) The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the IDENT and MFM bits 6 and 5 respectively of CRxx. PC/AT mode - (IDENT high, MFM a "don't care") The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (FINTR and DRQ can be hi Z), and TC and DENSEL become active high signals. 36 PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care" (FINTR and DRQ are always valid), TC and DENSEL become active low. Model 30 mode - (IDENT low, MFM low) This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of ther DOR becomes valid (FINTR and DRQ can be hi Z), TC is active high and DENSEL is active low. DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. The FDC37C93xAPM supports two DMA transfer modes for the FDC: Single Transfer and Burst Transfer. In the case of the single transfer, the DMA Req goes active at the start of the DMA cycle, and the DMA Req is deasserted after the nDACK. In the case of the burst transfer, the Req is held active until the last transfer (independent of nDACK). See timing diagrams for more information. Burst mode is enabled via Bit[1] of CRF0 in Logical Device 0. Setting Bit[1]=0 enables burst mode; the default is Bit[1]=1, for non-burst mode. CONTROLLER PHASES For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 19 for the command set descriptions.) These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. 37 Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, full sector have been placed in the FIFO. The FINT pin can be used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the FINT pin and RQM bit when the FIFO becomes empty. Non-DMA Mode - Transfers from the Host to the FIFO The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The FINT pin and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has 38 DMA Mode - Transfers from the Host to the FIFO The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active until the FIFO becomes full. FDRQ is again set true when the FIFO has complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. Result Phase The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively and the CB bit is cleared, indicating that the FDC is ready to accept the next command. 39 COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 19 for explanations of the various symbols used. Table 20 lists the required parameters and the results associated with each command that the FDC is capable of performing. Table 19 - Description of Command Symbols SYMBOL C D D0, D1, D2, D3 DIR DS0, DS1 NAME Cylinder Address Data Pattern Drive Select 0-3 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DS1 DS0 DRIVE 0 0 drive 0 0 1 drive 1 1 0 drive 2 1 1 drive 3 By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. Direction Control Disk Drive Select DTL Special Sector Size EC EFIFO EIS Enable Count Enable FIFO Enable Implied Seek 40 Table 19 - Description of Command Symbols SYMBOL EOT GAP GPL H/HDS HLT Gap Length Head Address Head Load Time NAME End of Track DESCRIPTION The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "Software Reset" (reset caused by writing to the appropriate bits of either tha DSR or DOR). MFM/FM Mode Selector Multi-Track Selector A "1" selects the double density (MFM) mode. A "0" selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. HUT Head Unload Time LOCK MFM MT 41 Table 19 - Description of Command Symbols SYMBOL N NAME Sector Size Code DESCRIPTION This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N 00 01 02 03 NCN ND New Cylinder Number Non-DMA Mode Flag SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes The desired cylinder number. When set to "1", indicates that the FDC is to operate in the nonDMA mode. In this mode, the host is interrupted for each data transfer. When set to "0", the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to "1". OW is defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. OW PCN POLL PRETRK Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address R The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. RCN Relative Cylinder Number 42 Table 19 - Description of Command Symbols SYMBOL SC NAME DESCRIPTION Number of The number of sectors per track to be initialized by the Format Sectors Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. Skip Flag When set to "1", sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. SK SRT Step Rate Interval The time interval between step pulses issued by the FDC Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbps data rate. Refer to the SPECIFY command for actual delays. Status 0 Status 1 Status 2 Status 3 Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular drives. Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. ST0 ST1 ST2 ST3 WGATE 43 INSTRUCTION SET Table 20 - Instruction Set READ DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 -------- C --------------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------- Data transfer between the FDD and system. Status information after Command execution. 44 READ DELETED DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 SK 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 0 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 -------- C --------------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------- Data transfer between the FDD and system. Status information after Command execution. 45 WRITE DATA DATA BUS PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------Sector ID information after Command execution. D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 1 REMARKS Command Codes Sector ID information prior to Command execution. HDS DS1 DS0 -------- C --------------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------- Data transfer between the FDD and system. Status information after Command execution. 46 WRITE DELETED DATA DATA BUS PHASE Command R/W W W W D7 MT 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 0 DS1 D0 1 DS0 Sector ID information prior to Command execution. REMARKS Command Codes -------- C -------- W W W W W W Execution Result R R R R R R R -------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------Data transfer between the FDD and system. ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------Sector ID information after Command execution. Status information after Command execution. 47 READ A TRACK DATA BUS PHASE Command R/W W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to Command execution. REMARKS Command Codes -------- C -------- W W W W W W Execution -------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------- DTL ------Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Result R R R R R R R ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------- Status information after Command execution. Sector ID information after Command execution. 48 VERIFY DATA BUS PHASE Command R/W W W W D7 MT EC D6 MFM 0 D5 SK 0 D4 1 0 D3 0 0 D2 1 HDS D1 1 DS1 D0 0 DS0 Sector ID information prior to Command execution. REMARKS Command Codes -------- C -------- W W W W W W Execution Result R R R R -------- H --------------- R --------------- N -------------- EOT ------------- GPL ------------ DTL/SC -----No data transfer takes place. Status information after Command execution. ------- ST0 ------------- ST1 ------------- ST2 -------------- C --------------- H --------------- R --------------- N -------- Sector ID information after Command execution. R R R VERSION DATA BUS PHASE Command Result R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 REMARKS Command Code Enhanced Controller 49 FORMAT A TRACK DATA BUS PHASE Command R/W W W W W W W Execution for Each Sector Repeat: W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters REMARKS Command Codes -------- N --------------- SC -------------- GPL -------------- D --------------- C -------- W W W -------- H --------------- R --------------- N -------FDC formats an entire cylinder Result R R R R R R R ------- ST0 ------------- ST1 ------------- ST2 ------------ Undefined ----------- Undefined ----------- Undefined ----------- Undefined ------ Status information after Command execution 50 RECALIBRATE DATA BUS PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 DS1 D0 1 DS0 Head retracted to Track 0 Interrupt. SENSE INTERRUPT STATUS DATA BUS PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 REMARKS Command Codes Status information at the end of each seek operation. REMARKS Command Codes ------- ST0 ------------- PCN ------SPECIFY DATA BUS PHASE Command R/W W W W D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 ND REMARKS Command Codes --- SRT --- --- HUT --- ------ HLT ------ 51 SENSE DRIVE STATUS DATA BUS PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 HDS D1 0 DS1 D0 0 DS0 Status information about FDD REMARKS Command Codes ------- ST3 ------- SEEK DATA BUS PHASE Command R/W W W W Execution D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Head positioned over proper cylinder on diskette. CONFIGURE DATA BUS PHASE Command R/W W W W Execution W D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 POLL D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure Information REMARKS Command Codes ------- NCN ------- EIS EFIFO --- FIFOTHR --- --------- PRETRK --------- 52 RELATIVE SEEK DATA BUS PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 REMARKS ------- RCN ------DUMPREG DATA BUS PHASE Command R/W W D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS *Note: Registers placed in FIFO Execution Result R R R R R R R R R R LOCK 0 0 ------ PCN-Drive 0 ------------ PCN-Drive 1 ------------ PCN-Drive 2 ------------ PCN-Drive 3 ---------- SRT ---------- HLT ------------- SC/EOT ------D3 D2 POLL D1 D0 GAP WGATE EIS EFIFO -- FIFOTHR ---- HUT --ND -------- PRETRK -------- 53 READ ID DATA BUS PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 HDS D1 1 DS1 D0 0 DS0 The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution. REMARKS Commands Result R R R R R R -------- ST0 --------------- ST1 --------------- ST2 --------------- C --------------- H --------------- R --------------- N -------- Disk status after the Command has completed 54 PERPENDICULAR MODE DATA BUS PHASE Command R/W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D0 D1 1 GAP D0 0 WGATE REMARKS Command Codes INVALID CODES DATA BUS PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid Command Codes (NoOp - FDC goes into Standby State) ST0 = 80H ----- Invalid Codes ----- Result R ------- ST0 ------LOCK DATA BUS PHASE Command Result R/W W R D7 LOCK 0 D6 0 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Codes SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). 55 DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "MultiSector Read Operation". Upon receipt of TC, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 21 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 21 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 22. 56 At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 23 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 23, the C or R value of the sector address is automatically incremented (see Table 25). MT 0 1 0 1 0 1 N 1 1 2 2 3 3 Table 22 - Effects of MT and N Bits FINAL SECTOR READ MAXIMUM TRANSFER FROM DISK CAPACITY 256 x 26 = 6,656 26 at side 0 or 1 256 x 52 = 13,312 26 at side 1 512 x 15 = 7,680 15 at side 0 or 1 512 x 30 = 15,360 15 at side 1 1024 x 8 = 8,192 8 at side 0 or 1 1024 x 16 = 16,384 16 at side 1 SK BIT VALUE 0 0 Table 23 - Skip Bit vs Read Data Command DATA ADDRESS MARK TYPE RESULTS ENCOUNTERED SECTOR CM BIT OF DESCRIPTION OF READ? ST2 SET? RESULTS Normal Data Yes No Normal termination. Deleted Data Yes Yes Address not incremented. Next sector not searched for. Normal termination. 1 1 Normal Data Deleted Data Yes No No Yes Normal termination. Sector not read ("skipped"). 57 Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 24 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 24, the C or R value of the sector address is automatically incremented (see Table 25). SK BIT VALUE 0 0 1 1 Table 24 - Skip Bit vs. Read Deleted Data Command DATA ADDRESS MARK TYPE RESULTS ENCOUNTERED SECTOR CM BIT OF DESCRIPTION READ? ST2 SET? OF RESULTS Normal Data Yes Yes Address not incremented. Next sector not searched for. Normal Deleted Data Yes No termination. Normal Normal Data No Yes termination. Sector not read ("skipped"). Normal Deleted Data Yes No termination. command and sets the ND flag of Status Register 1 to a "1" if there is no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the 58 MT 0 HEAD 0 1 Table 25 - Result Phase Table FINAL SECTOR ID INFORMATION AT RESULT PHASE TRANSFERRED TO HOST C H R N Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT NC C+1 NC C+1 NC NC NC C+1 NC NC NC NC NC LSB NC LSB R+1 01 R+1 01 R+1 01 R+1 01 NC NC NC NC NC NC NC NC 1 0 1 NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "MultiSector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: * Transfer Capacity * EN (End of Cylinder) bit * ND (No Data) bit * Head Load, Unload Time Interval * ID information when the host terminates the command * Definition of DTL when N = 0 and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark 59 a bad sector containing an error on the floppy disk. Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, TC (pin 89) cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 25 and Table 26 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". MT 0 0 0 0 1 1 1 1 EC 0 0 1 1 0 0 1 1 Table 26 - Verify Command Result Phase Table SC/EOT VALUE TERMINATION RESULT SC = DTL EOT # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC # Sectors Remaining AND EOT # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT # Sectors Per Side SC = DTL EOT > # Sectors Per Side SC # Sectors Remaining AND EOT # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side Success Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. 60 Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the IDX pin again and it terminates the command. Table 27 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S E C N O C R C GAP2 SYNC 22x 12x 4E 00 DATA AM DATA 3x FB A1 F8 C R C GAP3 GAP 4b 3x FC C2 3x FE A1 SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a 40x FF SYNC 6x 00 IAM GAP1 SYNC 26x 6x FF 00 IDAM C Y L H D S E C N O C R C GAP2 SYNC 11x 6x FF 00 DATA AM DATA FB or F8 C R C GAP3 GAP 4b FC FE PERPENDICULAR FORMAT GAP4a 80x 4E SYNC 12x 00 IAM GAP1 SYNC 50x 12x 4E 00 IDAM C Y L H D S E C N O C R C GAP2 SYNC 41x 12x 4E 00 DATA AM DATA 3x FB A1 F8 C R C GAP3 GAP 4b 3x FC C2 3x FE A1 61 FORMAT Table 27 - Typical Values for Formatting SECTOR SIZE N SC GPL1 128 128 512 1024 2048 4096 ... 256 256 512* 1024 2048 4096 ... 128 256 512 256 512** 1024 00 00 02 03 04 05 ... 01 01 02 03 04 05 ... 0 1 2 1 2 3 12 10 08 04 02 01 12 10 09 04 02 01 0F 09 05 0F 09 05 07 10 18 46 C8 C8 0A 20 2A 80 C8 C8 07 0F 1B 0E 1B 35 GPL2 09 19 30 87 FF FF 0C 32 50 F0 FF FF 1B 2A 3A 36 54 74 FM 5.25" Drives MFM 3.5" Drives FM MFM GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. NOTE: All values except sector size are in hex. 62 CONTROL COMMANDS Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTR0 pin from the FDD. As long as the nTR0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTR0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTR0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses. The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. 63 During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. b. c. d. e. f. g. h. Read A Track command Read ID command Read Deleted Data command Write Data command Format A Track command Write Deleted Data command Verify command 2. End of Seek, Relative Seek, or Recalibrate command 3. FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 28 - Interrupt Identification SE 0 1 IC 11 00 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command - The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command be issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command. Sense Interrupt Status An interrupt signal on FINT pin is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command 1 01 The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. 64 Sense Drive Status Sense Drive Status obtains drive status information. It has no execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speedselection and are documented in Table 29. The values are the same for MFM and FM. Table 29 - Drive Control Delays (ms) HUT SRT 2M 0 1 .. E F 64 4 .. 56 60 1M 128 8 .. 112 120 500K 256 16 .. 224 240 300K 426 26.7 .. 373 400 250K 512 32 .. 448 480 HLT 2M 00 01 02 .. 7F 7F 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 2M 4 3.75 .. 0.5 0.25 1M 8 7.5 .. 1 0.5 500K 16 15 .. 2 1 300K 26.7 25 .. 3.33 1.67 250K 32 30 .. 4 2 The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signalled by the FDRQ pin. NonDMA mode uses the RQM bit and the FINT pin to signal data transfers. 65 Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byteby-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte. Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control DIR 0 1 ACTION Step Head Out Step Head In RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved 66 with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 30 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown on Page 61 illustrates the change in the Gap2 field size for the perpendicular format. 67 On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown on page 62. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write precompensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. The write pre-compensation given to a perpendicular mode drive will be 0ns. 3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware following effect on the MODE COMMAND: resets have the PERPENDICULAR 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. 68 WGATE 0 0 1 1 Table 30 - Effects of WGATE and GAP Bits PORTION OF GAP 2 WRITTEN BY LENGTH OF GAP2 FORMAT WRITE DATA OPERATION FIELD MODE GAP 0 1 0 1 Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps) 22 Bytes 22 Bytes 22 Bytes 41 Bytes 0 Bytes 19 Bytes 0 Bytes 38 Bytes LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO, the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The FDC37C93xAPM was designed with software compatibility in mind. It is a fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS. 69 SERIAL PORT (UART) The FDC37C93xAPM incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-toparallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR infrared modes of operation. Note: The UARTs may be configured to share an interrupt. Refer to the Configuration section for more information. REGISTER DESCRIPTION Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The FDC37C93xAPM contains two serial ports, each of which contain a register set as described below. DLAB* 0 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 0 1 1 1 1 0 0 Table 31 - Addressing the Serial Port A1 A0 REGISTER NAME 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write) *Note: DLAB is Bit 7 of the Line Control Register 70 The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. INTERRUPT ENABLE REGISTER (IER) Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37C93xAPM. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. BIT 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". BIT 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". BIT 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. BIT 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. BIT 4 - 7 These bits are always logic "0". FIFO CONTROL REGISTER (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. BIT 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. 71 BIT 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing. BIT 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing. BIT 3 Writting to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. BIT 4 and 5 Reserved BIT 6 and 7 These bits are used to set the trigger level for the RCVR FIFO interrupt. INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. BIT 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. BIT 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. BIT 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. BIT 4 and 5 These bits of the IIR are always logic "0". BIT 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Bit 7 0 0 1 1 Bit 6 0 1 0 1 RCVR FIFO TRIGGER LEVEL (BYTES) 1 4 8 14 By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 72 Table 32 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1 BIT 0 1 0 PRIORITY LEVEL Highest INTERRUPT SET AND RESET FUNCTIONS INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available INTERRUPT RESET CONTROL Reading the Line Status Register 0 1 0 0 Second Received Data Available Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register 1 1 0 0 Second Character Timeout Indication No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Transmitter Holding Register Empty 0 0 1 0 Third Transmitter Holding Register Empty Reading the IIR Register (if Source of Interrupt) or Writing the Transmitter Holding Register Reading the MODEM Status Register 0 0 0 0 Fourth MODEM Status Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect 73 LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: BIT 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: BIT 1 0 0 1 1 BIT 0 WORD LENGTH 0 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits BIT 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). BIT 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. BIT 5 Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. BIT 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. BIT 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. MODEM CONTROL REGISTER (MCR) Address Offset = 4H, DLAB = READ/WRITE The Start, Stop and Parity bits are not included in the word length. BIT 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. NUMBER OF STOP BITS 1 1.5 2 2 2 BIT 2 0 1 1 1 1 WORD LENGTH -5 bits 6 bits 7 bits 8 bits Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. X, 74 This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. BIT 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". BIT 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. BIT 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. BIT 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. BIT 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1. 2. 3. The TXD is set to the Marking State (logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. 5. 6. 7. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. BIT 5 - 7 These bits are permanently set to logic "0". LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB READ/WRITE = X, BIT 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. BIT 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrunn error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately 4. 75 upon detection of an overrun condition, and reset whenever the Line Status Register is read. BIT 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. BIT 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. BIT 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. BIT 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least one byte is written to the XMIT FIFO. Bit 5 is a read- only bit. BIT 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty. BIT 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. 76 MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB READ/WRITE = X, This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. BIT 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. BIT 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. BIT 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". BIT 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. BIT 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. BIT 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. BIT 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. BIT 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR. SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of taking any clock input (DC to 3 MHz) and dividing it by any divisor from 1 to 65535. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for 77 the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 33 shows the baud rates possible with a 1.8462 MHz crystal. Effect Of The Reset on Register File The Reset Function Table (Table 34) details the effect of the Reset input on each of the registers of the Serial Port. FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will issued when the FIFO has reached programmed trigger level; it is cleared soon as the FIFO drops below programmed trigger level. be its as its - was longer than four continuous character times ago. (If two stop bits are programmed, the second one is included in this time delay.) The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300BAUD with a 12 bit character. B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: at least one character is in the FIFO The most recent serial character received 78 Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO POLLED MODE OPERATION - With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to "0" puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: - Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. 79 Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432 MHz Clock for 115.2k ; Using 3.6864 MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED DIVISOR USED TO PERCENT ERROR DIFFERENCE CRxx: BAUD RATE GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL* BIT 7 OR 6 50 2304 0.001 X 75 1536 X 110 1047 X 134.5 857 0.004 X 150 768 X 300 384 X 600 192 X 1200 96 X 1800 64 X 2000 58 0.005 X 2400 48 X 3600 32 X 4800 24 X 7200 16 X 9600 12 X 19200 6 X 38400 3 0.030 X 57600 2 0.16 X 115200 1 0.16 X 230400 32770 0.16 1 460800 32769 0.16 1 *Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%. 80 REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO Table 34 - Reset Function Table RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5, 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low High High High High All Bits Low All Bits Low 81 REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 Table 35 - Register Summary for an Individual UART Channel REGISTER REGISTER NAME SYMBOL BIT 0 Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register RBR THR IER Data Bit 0 (Note 1) Data Bit 0 Enable Received Data Available Interrupt (ERDAI) "0" if Interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Bit 8 BIT 1 Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit ADDR = 2 Interrupt Ident. Register (Read Only) IIR ADDR = 2 ADDR = 3 FIFO Control Register (Write Only) Line Control Register FCR LCR RCVR FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) ADDR = 4 MODEM Control Register MCR ADDR = 5 ADDR = 6 Line Status Register MODEM Status Register LSR MSR Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9 ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1 Scratch Register (Note 4) Divisor Latch (LS) Divisor Latch (MS) SCR DDL DLM *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. 82 Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) Interrupt ID Bit (Note 5) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Data Bit 4 Data Bit 4 0 Data Bit 5 Data Bit 5 0 Data Bit 6 Data Bit 6 0 Data Bit 7 Data Bit 7 0 0 0 FIFOs Enabled (Note 5) FIFOs Enabled (Note 5) Reserved Reserved RCVR Trigger RCVR Trigger LSB MSB Set Break Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Even Parity Select (EPS) Loop Stick Parity 0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13 0 Transmitter Empty (TEMT) (Note 2) Framing Error Break (FE) Interrupt (BI) Trailing Edge Delta Data Clear to Send Ring Indicator Carrier Detect (CTS) (TERI) (DDCD) Bit 2 Bit 2 Bit 10 Note 3: Note 4: Note 5: Note 6: Bit 3 Bit 3 Bit 11 Bit 4 Bit 4 Bit 12 Ring Indicator Data Carrier (RI) Detect (DCD) Bit 6 Bit 6 Bit 14 Bit 7 Bit 7 Bit 15 This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip. 83 NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO-related features allow optimization of CPU/UART transactions and are especially useful given the higer baud rate capability (256 kbaud). 84 INFRARED INTERFACE The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TX and RX pins or optional IRTX2 and IRRX2 pins. These can be selected through the configuration registers. IrDA allows serial communication at baud rates up to 115K Baud. Each word is sent serially beginning with a "0" value start bit. A "0" is signaled by sending a single IR pulse at the beginning of the serial bit time. A "1" is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR allows serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a "0" value start bit. A zero is signaled by sending a 500 kHz waveform for the duration of the serial bit time. A "1" is signaled by sending no transmission the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. 85 PARALLEL PORT The FDC37C93xAPM incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The FDC37C93xAPM also provides a mode for support of the floppy disk controller on the parallel port. DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer powerup. The functionality of the parallel port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the parallel port is shown below: EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H The bit map of these registers is: D0 D1 D2 D3 D4 D5 DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 STATUS TMOUT 0 0 nERR SLCT PE PORT CONTROL STROBE AUTOFD nINIT SLC IRQE PCD PORT EPP ADDR PD0 PD1 PD2 PD3 PD4 PD5 PORT EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PORT 0 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PORT 1 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PORT 2 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PORT 3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus. D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 AD7 PD7 PD7 PD7 PD7 Note 1 1 1 2,3 2,3 2,3 2,3 2,3 86 Table 36 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. PIN NUMBER STANDARD nStrobe PData<0:7> nAck Busy PE Select nAutofd nError nInit nSelectin nWrite PData<0:7> Intr nWait (NU) (NU) nDatastb (NU) (NU) nAddrstrb EPP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3) ECP 87 IBM XT/AT COMPATIBLE, BIDIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0-PD7 ports. During a READ operation in SPP mode, PD0-PD7 ports are buffered (not latched) and output to the host CPU. STATUS PORT ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 sec time out has occured on the EPP bus. A logic "0" means that no time out error has occured; a logic "1" means that a time out error has been detected. This bit is cleared by a RESET. Writing a "1" to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a "0". Writing a "0" to this bit has no effect. BIT 1 and 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic "0" means an error has been detected; a logic "1" means no error has been detected. BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic "1" means the printer is on line; a logic "0" means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic "1" indicates a paper end; a logic "0" indicates the presence of paper. BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic "0" means that the printer has received a character and can now accept another. A logic "1" means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic "0" in this bit means that the printer is busy and cannot accept a new character. A logic "1" means that it is ready to accept the next character. CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. 88 BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic "0" means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bidirectional, EPP or ECP mode, a logic "0" means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written. EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0DB7 are buffered (non inverting) and output onto the PD0-PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0-PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non-inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0-PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode. 89 EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10 sec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (ie a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus; no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive. 2. 90 Write Sequence of Operation 1. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the SData bus for the PData bus and asserts (releases) IOCHRDY allowing the host to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle. 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive. 2. 3. 4. 5. 2. Read Sequence of Operation 1. The host selects an EPP register and drives nIOR active. 2. The chip drives IOCHRDY inactive (low). 3. If WAIT is not asserted, the chip must wait until WAIT is asserted. 4. The chip tri-states the PData bus and deasserts nWRITE. 5. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 6. Peripheral drives PData bus valid. 7. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 8. a) The chip latches the data from the PData bus for the SData bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b) The chip drives the valid data onto the SData bus and asserts (releases) IOCHRDY allowing the host to complete the read cycle. 9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. 6. 7. 8. 9. EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 91 EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10 sec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip places address or data on PData bus. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. When the host deasserts nIOW the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. 2. 3. 4. 5. 6. 7. EPP 1.7 Read Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. The host selects an EPP register and drives nIOR active. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. The Peripheral drives PData bus valid. 2. 3. 4. 5. 92 6. 7. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. When the host deasserts nIOR the chip deasserts nDATASTB or nADDRSTRB. 8. 9. Peripheral tri-states the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. 93 Table 37 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP.) This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. write operation. It is used to denote data read or DATASTB RESET ADDRSTB PE SLCT nData Strobe nReset nAddress Strobe Paper End Printer Selected Status Error Parallel Port Direction O O O I I This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. or write operation. Same as SPP mode. Same as SPP mode. It is used to denote address read nERR PDIR I O Same as SPP mode. This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use one common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. 94 EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. * * * * * * * * High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers Permits the use of adaptive signal timing Peer-to-peer capability reverse: Peripheral to Host communication Pword: A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8 bits. 1 A high level. 0 A low level. These terms may be considered synonymous: * * * * * * * * * PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Vocabulary The following terms are used in this document: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: Host to Peripheral communication. assert: Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is shown in the table on the following page. 95 D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 compress PD7 Addr/RLE nBusy 0 D6 PD6 D5 PD5 D4 PD4 D3 PD3 D2 PD2 D1 PD1 D0 PD0 Note Address or RLE field nAck 0 PError Direction Select ackIntEn nFault SelectIn 0 nInit 0 autofd 0 strobe 2 1 1 2 2 2 Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 intrValue MODE 0 1 Parallel Port IRQ nErrIntrEn dmaEn 0 0 0 Parallel Port DMA serviceIntr full empty 0 Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth ISA IMPLEMENTATION STANDARD channel that supports DMA for ECP in both the forward and reverse directions. This specification describes the standard ISA interface to the Extended Capabilities Port Small FIFOs are employed in both forward and (ECP). All ISA devices supporting ECP must reverse directions to smooth data flow and meet the requirements contained in this section improve the maximum bandwidth requirement. or the port will not be supported by Microsoft. The size of the FIFO is 16 bytes deep. The port For a description of the ECP Protocol, please supports an automatic handshake for the refer to the IEEE 1284 Extended Capabilities standard parallel port to improve compatibility Port Protocol and ISA Interface Standard, Rev. mode transfer speed. 1.14, July 14, 1993. This document is available from Microsoft. The port also supports run length encoded (RLE) decompression (required) in hardware. Description Compression is accomplished by counting identical bytes and transmitting an RLE byte The port is software and hardware compatible that indicates how many times the next byte is with existing parallel ports so that it may be to be repeated. Decompression simply used as a standard LPT port if ECP is not intercepts the RLE byte and repeats the required. The port is designed to be simple and following byte the specified number of times. requires a small number of gates to implement. Hardware support for compression is optional. 96 NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I Table 38 - ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode. PError (nAckReverse) I Select nAutoFd (HostAck) I O nFault (nPeriphRequest) I nInit O nSelectIn O 97 Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr Table 39 - ECP Register Definitions ADDRESS (Note 1) ECP MODES +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 40 - Mode Descriptions DESCRIPTION* SPP mode PS/2 Parallel Port mde Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) (Reserved) Test mode Configuration mode MODE 000 001 010 011 100 101 110 111 *Refer to ECR Register Description 98 DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0-PD7 ports. During a READ operation, PD0-PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is ony defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet. DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits 0-2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register. BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. 99 BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is reread again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. 100 Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h are written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read-only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value on the ISA IRQ line to determine possible conflicts. BITS 3 - 0 Parallel Port IRQ Refer to Table 41B. BITS 2 - 0 Parallel Port DMA Refer to Table 41C. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7 - 5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a "1" to a "0". This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is 0). 0: Disables DMA unconditionally. BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following three cases of interrupts. Once one of the three service interrupts has occurred serviceIntr bit shall be set to a "1" by hardware. It must be reset to "0" to re-enable the interrupts. Writing this bit to a "1" will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a "1" when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. 101 BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least one free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least one byte of data. 102 R/W 000: Table 41A - Extended Control Register MODE Standard Parallel Port Mode. In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register L3-CRF0. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). Table 41C CONFIG REG B BITS 2:0 DMA SELECTED 3 2 1 All Others 011 010 001 000 001: 010: 011: 100: 101: 110: 111: Table 41B CONFIG REG B IRQ SELECTED BITS 5:3 15 14 11 10 9 7 5 All Others 110 101 100 011 010 001 111 000 103 OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: * * * * Set Direction = 0, enabling the drivers. Set strobe = 0, causing the nStrobe signal to default to the deasserted state. Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. 104 Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 42 Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 D[6:0] 0 1 Run-Length Count (0-127) (mode 0011 0X00 only) Channel Address (0-127) is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. ISA Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section.) Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware 105 Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. 3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. 4. When ackIntEn is 1 and the nAck signal transitions from a low to a high. FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received. 2. For Programmed I/O: a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. b. (1) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are 106 DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle.) Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. 107 The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold = (16- the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16- An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16- 108 PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the Parallel Port Mode Register, as defined in the Parallel Port Mode Register, Logical Device 3, at 0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins. When the PPFDC is selected the following pins are set as follows: 1. 2. 3. nPDACK: high-Z PDRQ: not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z PINTR: not active, this is hi-Z or Low depending on settings. nPDACK, PDRQ and PINTR refer to the nDACK, DRQ and IRQ chosen for the parallel port. The following parallel port pins are read as follows by a read of the parallel port register: 1. 2. Data Register (read) = last Data Register (write) Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1 Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1. 3. The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select register: 1. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1. If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is selected. 2. Note: The FDC signals are muxed onto the Parallel Port pins as shown in Table 43. 109 Table 43 - FDC Parallel Port Pins CONNECTOR PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CHIP PIN # 144 138 137 136 135 134 133 132 131 129 128 127 126 143 142 141 140 SPP MODE nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN PIN DIRECTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O FDC MODE (nDS0) nINDEX nTRK0 nWP nRDATA nDSKCHG nMEDIA_ID0 (nMTR0) MEDIA_ID1 nDS1 nMTR1 nWDATA nWGATE DRVDEN0 nHDSEL nDIR nSTEP PIN DIRECTION I/(O) (Note1) I I I I I I I/(O) (Note1) I O O O O O O O O Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1. 110 AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23B0. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1. 2. The motor enable pins of register 3F2H are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The head unload timer must have expired. The auto powerdown timer (10msec) must have timed out. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective. Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the RESET pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1. An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the data register. 3. 4. 2. 3. Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. 111 Register Behavior Table 44 reiterates the AT and PS/2 (including Model 30) configuration registers available. It also shows the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 44 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it. Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. Pin Behavior The FDC37C93xAPM is specifically designed for portable PC systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the FDC37C93xAPM can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. System Interface Pins Table 45 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the FDC37C93xAPM when they have indeterminate input values. 112 Table 44 - PC/AT and PS/2 Available Registers Available Registers Base + Address 00H 01H 02H 03H 04H 06H 07H 07H 04H 05H PC-AT ------DOR (1) --DSR (1) --DIR CCR MSR Data PS/2 (Model 30) SRA SRB DOR (1) --DSR (1) --DIR CCR MSR Data Access Permitted R R R/W --W --R W R R/W Access to these registers DOES NOT wake up the part Access to these registers wakes up the part Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. Table 45 - State of System Pins in Auto Powerdown SYSTEM PINS STATE IN AUTO POWERDOWN Input Pins IOR IOW A[0:9] D[0:7] RESET IDENT DACKx TC IRQx DB[0:7] DRQx Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Output Pins Unchanged (low) Unchanged Unchanged (low) 113 FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 46 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS STATE IN AUTO POWERDOWN Input Pins RDATA WP TRK0 INDX DRV2 DSKCHG Output Pins MOTEN[0:3] DS[0:3] DIR STEP WRDATA WE HDSEL DENSEL DRATE[0:1] Tristated Tristated Active Active Tristated Tristated Active Active Active Input Input Input Input Input Input 114 UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: A. Receive FIFO is empty B. The receiver is waiting for a start bit. Parallel Port Direct power management is controlled by CR22. Refer to CR22 for more information. Auto power management is enabled by CR23B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following conditions: 1. 2. EPP is not enabled in the configuration registers. EPP is not selected through ecr while in ECP mode. 2. Note: While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes. Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state. The ECP logic is in powerdown under any of the following conditions: 1. 2 ECP is not enabled in the configuration registers. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. 115 INTEGRATED DRIVE ELECTRONICS INTERFACE The FDC37C93xAPM contains two IDE interfaces. This enables hard disks with embedded controllers (AT or IDE) to be interfaced to the host processor. The IDE interface performs the address decoding for the IDE interface, generates the buffer enables for external buffers and provides internal buffers for the low byte IDE data transfers. For more information, refer to the IDE pin descriptions and the ATA specification. The following example uses IDE1 base1=1F0H, base2=3F6H and IDE2 base1=170H, base2 =376H. HOST FILE REGISTERS The Host File Registers are accessed by the AT Host. There are two groups of registers, the AT Task File, and the Miscellaneous AT Register. ADDRESS 1F0H-1F7H; 170H-177H These AT registers contain the Task File Registers. These registers communicate data, command, and status information with the AT host, and are addressed when nHCS0 or nHCS2 is low. ADDRESS 3F6H/376H; These AT registers may be used by the BIOS for drive control. They are accessed by the AT interface when nHCS1 or nHCS3 is active low. HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE) PRIMARY 1F0H | 1F7H 3F6H TASK FILE REGISTERS Task File Registers may be accessed by the host AT when pin nHDCS0 is active (low). The Data Register (1F0H) is 16 bits wide; the remaining task file registers are 8 bits wide. The task file registers are ATA and EATA compatible. Please refer to the ATA SECONDARY 170H | 177H 376H MISC AT REGISTERS and EATA specifications. These are available from: Global Engineering 2805 McGaw Street Irvine, CA 92714 (800) 854-7179 or (714) 261-1455 TASK FILE REGISTERS 116 IDE OUTPUT ENABLES Two IDE output Enables are available. The IDE output enables treat all IDE transfers as 16 bit transfers. nIDE1_OE Option 1 Option 2 Note 1: Note 2: Note 3: IDE1 (1) IDE1&IDE2 (3) nIDE2_OE IDE2 (2) (Not used) The low and high byte transfers for IDE1 goes through external buffers controlled by IDE1_OE. (Refer to Option 1) The low and high byte transfers for IDE2 goes through external buffers controlled by IDE2_OE. (Refer to Option 1) The low and high byte transfers of IDE1 and IDE2 go through one set of external buffers controlled by IDE1. (Refer to Option 2) configured to support IDE drives, can be programmed as general purpose address decoders. Refer to the Configuration Register Section, Logical Device 1, CRF0 and CRF1. HDCS0 and HDCS1 of IDE1 as General Purpose Address Decoders HDCS0 and HDCS1 of IDE1, initially 117 BIOS BUFFER The FDC37C93xAPM contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS and nROMDIR must be tied high so as not to interfere with the boot ROM. This function allows data transmission from the RD bus to the SD bus or from the SD bus to the RD bus. The direction of the transfer is controlled by nROMDIR. The enable input, nROMCS, can be used to disable the transfer and isolate the buses. nROMCS L L H nROMDIR L H X RD[0:7] data to SD[0:7] bus SD[0:7] data to RD[0:7] Isolation SD[15:8] IDE Channel 1 FDC37C93xAPM SD[7:0] IDE1_OE B1 BIOS Option 1 IDE2_OE IDE Channel 2 FIGURE 2 - IDE OUTPUT ENABLE OPTION 1 118 SD[15:8] IDE Channel 1 FDC37C93xAPM SD[7:0] B1 IDE1_OE BIOS Option 2 IDE2_OE NC IDE Channel 2 FIGURE 3 - IDE OUTPUT ENABLE OPTION 2 119 RD Bus Functionality The following four cases described below illustrate the use of the RD Bus. Case 1: nROMCS and nROMOE as original function. The RD bus can be used as the RD bus or one or more RD pins can be programmed as alternate function. These alternate functions behave as follows: if in RD to SD mode, any value on RDx will appear on SDx; if in SD to RD mode, SDx will not appear on RDx, RDx gets the alternate function value. Note: In this case, nROMCS=0, nROMOE=1. Case 2: nROMOE as alternate function (nROMOE internally tied to ground). In this case, the RD bus is a unidirectional bus (read only) controlled by nROMCS. If nROMCS = 0, the values on RD0-7 appear on SD0-7. If nROMCS = 1, the RD bus is disabled and nothing appears on the SD bus. Note: any RD bus pin can be programmed as an alternate function, however, if nROMCS=0, then anything on the RD bus will appear on the SD bus. Case 3: nROMCS as alternate function (nROMCS internally tied to VDD). The RD bus floats - cannot use as a bus. Any pin can be programmed as an alternate function. Case 4: nROMCS and nROMOE as alternate function. Same as Case 3. 8042 Functions The second alternate function for pins 113-118 are the 8042 functions P12-P17. These are implemented as in a true 8042 part. Reference the 8042 specification for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. After several (# TBD) clocks, the port enable goes away and the internal 90A pull-up maintains the output signal as 1. In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared i.e., P12 and nSMI can be externally tied together. In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers. 120 GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION The FDC37C93xAPM provides a set of flexible Input/Output control functions to the system designer through a set of General Purpose I/O pins (GPI/O). These GPI/O pins may perform simple I/O or may be individually configured to provide a predefined alternate function. Poweron reset configures all GPI/O pins as simple non-inverting inputs. General Purpose I/O Ports The FDC37C93xAPM has 14 dedicated, independently-programmable general purpose I/O ports (GPI/O). Each GPI/O port is represented as a bit in one of two GPI/O 8-bit registers, GP1 or GP2. Only 6 bits of GP2 are implemented. Each GPI/O port and its alternate function is listed in Table 47A. Pin Number 96 97 98 99 100 102 103 104 105 106 107 108 109 Table 47A - General Purpose I/O Port Assignments Original Alternate Alternate Alternate Function Function 1 Function 2 Function 3 GP10 Interrupt Steering* GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 Interrupt Steering* WD Timer Output Power LED GP Address Decoder GP Write Strobe Joystick RD Strobe Joystick WR Strobe IDE2 Buffer Enable Serial EEPROM Data In * Serial EEPROM Data Out Serial EEPROM Clock Serial EEPROM Enable IRQ 13 IRRX Input IRTX Output Joystick Chip Sel 8042 P20 AB_DATA AB_CLK - Register Assignment GP1, bit 0 GP1, bit 1 GP1, bit 2 GP1, bit 3 GP1, bit 4 GP1, bit 5 GP1, bit 6 GP1, bit 7 GP2, bit 0 GP2, bit 1 GP2, bit 2 GP2, bit 3 GP2, bit 4 110 GP25 8042 P21 GP2, bit 5 Note 1: 8042 P21 is normally used for Gate A20 Note 2: 8042 P20 is normally used for the Keyboard Reset Output * These are input-type alternate functions; all other GPI/O pins contain output-type alternate functions. 121 The FDC37C93xAPM also has 28 GPI/O ports that are the first alternate functions of pins with other default functions. listed in Table 47B below. These pins are Table 47B - Multifunction GPI/O Pins PIN NUMBER 19 20 23 24 25 26 30 31 33 34 111 112 113 114 115 116 117 118 119 120 153 154 155 156 ORIGINAL FUNCTION MEDIA_ID1 MEDIA_ID0 nIDE1_OE nHDCS0 nHDCS1 IDE1_IRQ nIOROP nIOWOP nPowerOn Button_In RD0 (1) (3) RD1 (1) (3) RD2 (1) (3) RD3 (1) (3) RD4 (1) (3) RD5 (1) (3) RD6 (1) (3) RD7 (1) (3) nROMCS (1) nROMOE (1) nRI2 (2) nDCD2 (2) RXD2 (2) TXD2 (2) (3) ALTERNATE FUNCTION 1 GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP51 GP50 GP60 GP61 GP62 GP63 GP64 GP65 GP66 GP67 GP53 GP54 GP70 GP71 GP72 GP73 ALTERNATE FUNCTION 2 Power LED Output nSMI Power LED Output WDT 8042 - P12 8042 - P13 8042 - P14 8042 - P15 8042 - P16 8042 - P17 ALTERNATE FUNCTION 3 WDT GPI/O REGISTER ASSIGNMENT GP4, bit 0 GP4, bit 1 GP4, bit 2 GP4, bit 3 GP4, bit 4 GP4, bit 5 GP4, bit 6 GP4, bit 7 GP5, bit 1 GP5, bit 0 GP6, bit 0 GP6, bit 1 GP6, bit 2 GP6, bit 3 GP6, bit 4 GP6, bit 5 GP6, bit 6 GP6, bit 7 GP5, bit 3 GP5, bit 4 GP7, bit 0 GP7, bit 1 GP7, bit 2 GP7, bit 3 122 PIN NUMBER 157 158 159 160 ORIGINAL FUNCTION nDSR2 (2) nRTS2 (2) (3) nCTS2 (2) nDTR2 (2) (3) ALTERNATE FUNCTION 1 GP74 GP75 GP76 GP77 ALTERNATE FUNCTION 2 - ALTERNATE FUNCTION 3 - GPI/O REGISTER ASSIGNMENT GP7, bit 4 GP7, bit 5 GP7, bit 6 GP7, bit 7 Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0RD7 for functions other than the XD Bus, nROMCS must stay high until those pins are finished being reprogrammed. Note 2: These pins are input (high-z) until programmed for second serial port. Note 3: These pins cannot be programmed as open drain pins in their original function. Note 4: No pins in their original function can be programmed as inverted input or inverted output. GPI/O registers GP1 through GP7 as well as the Soft Power and SMI Enable and Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses an Index and Data register to access these registers. The Power on default Index and Data registers are 0xEA and 0xEB respectively. In configuration mode the Index address may be programmed to reside on addresses 0xE0, 0xE2, 0xE4 or 0xEA. The Data address is automatically set to the Index address + 1. Upon exiting the configuration mode the new Index and Data registers are used to access registers GP1 through GP7 and Soft Power and SMI Enable and Status Registers. To access the GP1 register when in normal (run) mode, the host should perform an IOW of 0x01 to the Index register (at 0xEX) to select GP1 and then read or write the Data register (at Index+1) to access the GP1 register. To access GP2 the host should perform an IOW of 0x02 to the Index register and then access GP2 through the Data register. GP4-7 and the Soft Power and SMI Registers are acessed similarly. Additionally the host can access the WDT_CTRL (Watch Dog Timer Control) Configuration Register while in the normal (run) mode by writing an 0x03 to the index register. The GP registers can also be accessed by the host when in configuration mode through CRF6FB of Logical Device 8. 123 REGISTER Index Data Table 48A - Index and Data Register ADDRESS NORMAL (RUN) MODE 0xE0, E2, E4, EA Index address + 1 0x01-0x0F Access to GP1, GP2, Watchdog Timer Control, GP4, GP5, GP6, GP7, Soft Power and SMI Enable and Status Registers (see Table 48B) Table 48B - Index and Data Register Normal (Run) Mode INDEX NORMAL (RUN) MODE 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Access to GP1 (L8 - CRF6) Access to GP2 (L8 - CRF7) Access to Watchdog Timer Control (L8 - CRF4) Access to GP4 (L8 - CRF8) Access to GP5 (L8 - CRF9) Access to GP6 (L8 - CRFA) Access to GP7 (L8 - CRFB) Access to Soft Power Enable Register 1 (L8-CRB0) Access to Soft Power Enable Register 2 (L8-CRB1) Access to Soft Power Status Register 1 (L8-CRB2) Access to Soft Power Status Register 2 (L8-CRB3) Access to SMI Enable Register 1 (L8-CRB4) Access to SMI Enable Register 2 (L8-CRB5) Access to SMI Status Register 1 (L8-CRB6) Access to SMI Status Register 2 (L8-CRB7) Note 1: These registers can also be accessed through the configuration registers at L8 CRxx shown in the table above. 124 GPI/O ports contain alternate functions which are either output-type or input-type. The GPI/O port structure for each type is illustrated in the following two figures. Note: the input pin buffer is always enabled. GPI/O Configuration Register bit-1 (Polarity) GPI/O Configuration Register bit-0 (Input/Output) SD-bit D-TYPE nIOW 0 nIOR Transparent GPI/O Pin 1 0 1 GPI/O Register Bit-n GPIO Configuration Register bit-3 (Alt Function) GPI/O Configuration Register bit-2 (Int En) Alternate Input Function To GP Interrupt FIGURE 4 - GPI/O HAVING AN INPUT-TYPE ALTERNATE FUNCTION [GP10, GP11, GP12, GP21] 125 GPIO Configuration Register bit-3 (Alt Function) Alternate Output Function GPI/O Configuration Register bit-1 (Polarity) GPI/O Configuration Register bit-0 (Input/Output) 1 SD-bit nIOW D-TYPE 0 0 nIOR Transparent GPI/O Pin 1 0 1 GPI/O Register Bit-n GPI/O Configuration Register bit-2 (Int En) To GP Interrupt FIGURE 5 - GPI/O HAVING AN OUTPUT-TYPE ALTERNATE FUNCTION [GP12 - GP17, GP20, GP22 - GP25] 126 General Purpose I/O Configuration Registers Assigned to each GPI/O port is an 8-bit GPI/O Configuration Register which is used to independently program each I/O port. The GPI/O Configuration Registers are only accessible when the FDC37C93xAPM is in the Configuration Mode; more information can be found in the Configuration section of this specification. Each GPI/O port may be programmed as either a simple inverting or non-inverting input or output port, or as an alternate function port. The least-significant four bits of each GPI/O Configuration Register define the operation of the respective GPI/O port. The basic GPI/O operations are outlined in Table 49. In addition, the GPI/O port may be optionally programmed to steer its signal to a Combined General Purpose Interrupt request output pin on the FDC37C93xAPM. The interrupt channel for the Combined Interrupt is selected by the GP_INT Configuration Register defined in the FDC37C93xAPM System Configuration Section. The Combined Interrupt is the "ORed" function of the interrupt enabled GPI/O ports and will represent a standard ISA interrupt (edge high). When programmed as an input steered onto the General Purpose Combined Interrupt (GP IRQ), the Interrupt Circuitry contains a selectable debounce/digital filter circuit in order that switches or push-buttons may be directly connected to the chip. This filter will reject signals with pulse widths of 1ms or less. Table 49 - GPI/O Configuration Register Bits [3:0] ALT FUNC BIT 3 0= DISABLE 1=SELECT 0 0 0 0 0 0 0 0 1 INT EN BIT 2 0=DISABLE 1=ENABLE 0 0 0 0 1 1 1 1 0 POLARITY BIT 1 0= NO INVERT 1=INVERT 0 0 1 1 0 0 1 1 0 I/O BIT 0 1=INPUT 0=OUTPUT 0 1 0 1 0 1 0 1 0 GPI/O PORT OPERATION simple non-inverting output simple non-inverting input simple inverting output simple inverting input non-inverting output steered back to GP IRQ non-inverting input steered to GP IRQ inverting output steered back to GP IRQ inverting input steered to GP IRQ Alternate Function Output-type: Alternate non-inverted output. Alternate Function Input-type: Alternate function not valid, GPI/O pin acts as a simple non-inverting output. 127 Table 49 - GPI/O Configuration Register Bits [3:0] ALT FUNC BIT 3 0= DISABLE 1=SELECT 1 INT EN BIT 2 0=DISABLE 1=ENABLE 0 POLARITY BIT 1 0= NO INVERT 1=INVERT 0 I/O BIT 0 1=INPUT 0=OUTPUT 1 GPI/O PORT OPERATION Alternate Function Output-type: Alternate function not valid, GPI/O pin acts as a simple non-inverting input. Alternate Function Input-type: Alternate non-inverting input. Alternate Function Output-type: Alternate output function with inverted sense Alternate Function Input-type: Alternate function not valid, GPI/O pin acts as a simple inverting output. Alternate Function Output-type: Alternate output function not valid, GPI/O pin acts as a simple inverting input. Alternate Function Input-type: Inverting input to alternate input function. Alternate Function Output-type: Alternate output function with non inverted sense steered to GP IRQ Alternate Function Input-type: Alternate function not valid, GPI/O pin acts as a simple non-inverting output steered to GP IRQ Alternate Function Output-Type: Alternate output function not valid, GPI/O pin acts as a simple non-inverting input steered to GP IRQ. Alternate Function Input-type: Non-inverting input to alternate input function also steered to the GP IRQ. 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 128 Table 49 - GPI/O Configuration Register Bits [3:0] ALT FUNC BIT 3 0= DISABLE 1=SELECT 1 INT EN BIT 2 0=DISABLE 1=ENABLE 1 POLARITY BIT 1 0= NO INVERT 1=INVERT 1 I/O BIT 0 1=INPUT 0=OUTPUT 0 GPI/O PORT OPERATION Alternate Function Output-type: Alternate output function with inverted sense steered to GP IRQ Alternate Function Inputtype:Alternate function not valid, GPI/O pin acts as a simple inverting output steered to GP IRQ. Alternate Function Output-type: Alternate output function not valid, GPI/O pin acts as a simple inverting input steered to GP IRQ. Alternate Function Input-type: Inverting input to alternate input function also steered to the GP IRQ. 1 1 1 1 The alternate function of GP10 and GP11 allows these GPI/O port pins to be mapped to their own independent interrupt channels. The upper nibble of the GP10 and GP11 GPI/O configuration registers is used to select the active interrupt channel for each of these ports as shown in the Configuration section of this specification. 129 Reading and Writing GPI/O Ports When a GPI/O port is programmed as an input, reading it through the GPI/O register latches either the inverted or non-inverted logic value present at the GPI/O pin; writing it has no effect. When a GPI/O port is programmed as an output, the logic value written into the GPI/O register is either output to or inverted to the GPI/O pin; when read the result will reflect the contents of the GPI/O register bit. This is summarized in Table 50. HOST OPERATION Read Write Table 50 - GPI/O Read/Write Behavior GPI/O INPUT PORT GPI/O OUTPUT PORT Latched Value of GPI/O Pin No Effect Bit Value In GP Register Bit Placed In GP Register WATCH DOG TIMER/POWER LED CONTROL BASIC FUNCTIONS The FDC37C93xAPM contains a Watch Dog Timer (WDT) and also has the capability to directly drive the system's Power-on LED. The Watch Dog Time-Out status bit (WDT_CTRL bit 0) is mapped to GP12 when the alternate function bit of the GP12 Configuration Register is set "and" bit 6 of the IR Options Register = 0. In addition, the Watch Dog Timeout status bit may be mapped to an interrupt through the WDT_CFG Configuration Register. Pins 30 (nIOROP/GP46) and 112 (RD1/GP61) can also be configured for WDT. GP13 may be configured as a high current LED driver to drive the power LED. This is accomplished by setting the alternate function bit of the GP13 Configuration Register "and" clearing bit 6 of the IR Options Register. The infared signals, IRRX and IRTX, are mapped to GP12 and GP13 when the alternate function bit of the GP12 and GP13 Configuration Registers is set "and" bit 6 of the IR Options Register is set. Pins 30 (nIOROP/GP46) and 111 (RD0/GP60) can also be configured for Power LED. WATCH DOG TIMER The FDC37C93xAPM's WDT has a programmable time-out ranging from one to 255 minutes with one minute resolution, or one to 255 seconds with one second resolution. The units of the WDT timeout value are selected via bit 7 of the GPA_GPW_EN register (located at 0xF1 of Logical Device 8). The WDT time-out value is set through the WDT_VAL Configuration register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Configuration Register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. 130 There are three system events which can reset the WDT; these are a keyboard interrupt, a mouse interrupt, or I/O reads/writes to address 0x201 (the internal or an external joystick Port). The effect on the WDT for each of these system events may be individually enabled or disabled through bits in the WDT_CFG Configuration Register. When a system event is enabled through the WDT_CFG register, the occurence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the WDT time-out status bit if set. If all three system events are disabled, the WDT will inevitably time out. The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Configuration Register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit. When the polarity bit is 0, GP12 reflect the value of the Watch Dog Time-out status bit, however when the polarity bit is 1, GP12 reflects the inverted value of the Watch Dog time-out status bit. This is also true for the other two pins used for WDT, nIOROP (GP46) and RD1 (GP61). The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Configuration Register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing. POWER LED TOGGLE Setting bit 1 of the WDT_CTRL Configuration Register will cause the power LED output driver to toggle at 1 Hertz with a 50 percent duty cycle. When this bit is cleared the power LED output will drive continuously unless it has been configured to toggle on Watch Dog time-out conditions. Setting bit 3 of the WDT_CFG configuration register will cause the Power LED output driver to toggle at 1 Hertz with a 50 percent duty cycle whenever the WDT time-out status bit is set. The truth table below clarifies the conditions for which the Power LED will toggle. When the polarity bit is 0, the power LED output asserts or drives low. If the polarity bit is 1 then the power LED output asserts or drives high. WDT_CTRL BIT 1 POWER LED TOGGLE 1 0 0 0 Table 51 - LED Toggle Truth Table WDT_CFG BIT 3 POWER LED WDT_CTRL BIT 0 TOGGLE ON WDT WDT T/O STATUS BIT X 0 1 1 X X 0 1 POWER LED STATE Toggle Continuous Continuous Toggle 131 Table 52 - Watchdog Timer/Power LED Configuration Registers CONFIG REG. BIT FIELD DESCRIPTION WDT_VAL WDT_CFG Bits[7:0] Bit[0] Bit[1] Bit[2] Bit[3] Bits[7:4] WDT_CTRL Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5,6,7] Binary coded time-out value, 0x00 disables the WDT. Joystick enable Keyboard enable Mouse enable Power LED toggle on WDT time-out WDT interrupt mapping, 0000b = diables irq mapping WDT time-out status bit Power LED toggle Force Timeout, self-clearing P20 Force Timeout Enable Reserved, set to zero Stop_Cnt, Restart_Cnt, SPOFF: used for Soft power mgt GENERAL PURPOSE WRITE General Purpose I/O pin GP15 may be configured as a General Purpose Write pin. The General Purpose Write provides an output decoded from the 12-bit address stored in a two-byte Base I/O Address Register (Logical Device 8 Configuration Registers 0x62, 0x63) qualified with IOW and AEN. This General Purpose output is normally active low, however the polarity may be altered through the polarity bit in its GPI/O Configuration Register. The GPA_GPW_EN Configuration Register contains two bits which allow the General Purpose Address Decode and Write functions to be independently enabled or disabled. JOYSTICK CONTROL The base I/O address of the Joystick (Game) Port is fixed at address 0x201. GENERAL PURPOSE ADDRESS DECODER General Purpose I/O pin GP14 may be configured as a General Purpose Address Decode Pin. The General Purpose Address Decoder provides an output decoded from bits A11-A1 of the 12-bit address stored in a twobyte Base I/O Address Register (Logical Device 8 Configuration Registers 0x60, 0x61) qualified with AEN. Thus, the decoder provides a two address decode where A0=X. This General Purpose output is normally active low, however the polarity may be altered through the polarity bit in its GPI/O Configuration Register. The pins nHDCS0 and nHDCS1 can also be used as general purpose address decoders. See Configuration section, Logical Device 1, for more information. 132 GP16 JOYSTICK FUNCTION The FDC37C93xAPM may be configured to generate either a Joystick Chip Select or a Joystick Read Strobe on GP16. The polarity is programmable through a bit in the GP16 confiugration register. When configured as a Joystick Chip Select the output is simply a decode of the address = 0x201 qualified by AEN active. When configured as a Joystick Read Strobe the output is a decode of the address = 0x201 qualified by IOR and AEN both active. The Joystick Chip Select or Read Strobe is normally active low, however its polarity is programmable through a bit in the GP20 configuration register. GP17 JOYSTICK FUNCTION The FDC37C93xAPM may be configured to generate a Joystick Write Strobe on GP17. When configured as a Joystick Write Strobe the output is a decode of the address = 0x201 qualified by IOW and AEN both active. The Joystick Write Strobe is normally active low, however, its polarity is programmable through a bit in the GP20 configuration register. IDE2 BUFFER ENABLE/RESET OUT The FDC37C93xAPM may be configured to provide an nIDE2_OE buffer enable signal on pin GP20. The IDE2 Mode Register (0xF0 of Logical Device 2) contains a bit which determines whether nIDE1_OE or nIDE2_OE is active for IDE2 transfers. If GP20 is selected as a General Purpose I/O pin, IDE2 I/O accesses must be configured to activate nIDE1_OE for IDE2 transfers if a secondary hard drive interface is present. The polarity of nIDE2_OE, which is normally active low, is programmable through a bit in the GP20 configuration register. SERIAL EEPROM INTERFACE Four of the FDC37C93xAPM's general purpose I/O pins may be configured to provide a four wire direct interface to a family of industry standard serial EEPROMs. For proper operation the polarity bits of these four pins must be set to 0 (non-inverting). The interface is depicted below and will allow connection to either a 93C06 (256-bit), a 93C46 (1K-bit), a 93C56 (2K-bit), or a 93C66 (4K-bit) device. GP21 <---- Serial EEPROM Data In GP22 ----> Serial EEPROM Data Out GP23 ----> Serial EEPROM Clock GP24 ----> Serial EEPROM Enable Reset out is an internal signal from the keyboard controller (Port 20). The FDC37C93xAPM may be configured to drive this signal onto GP20 by programming its GPI/O configuration register. Access to the serial EEPROM is only available when the FDC37C93xAPM is in the configuration mode. A set of six configuration registers, located in Logical Device 6 (RTC) is used to fully access and configure the serial EEPROM. The registers are defined as follows: Serial EEPROM Mode Register, 0xF1 BIT 3 and 0 These are the lock bits which once set deny access to the serial EEPROM's first 128 bytes in 32 byte blocks. Bit 0 locks the first block, bit 1 the second block, bit 2 the third block and bit 3 the fourth block of 32 bytes. Once these lock bits are set they cannot be reset in any way other than by a Hard reset or a power-on reset. BIT 4 This selects the type of EEPROM connected to the FDC37C93xAPM. If cleared the device must be either a 93C06 or 93C46 and if set the device must be either an 93C56 or 93C66. This bit must be properly set before attempting to access the serial EEPROM. 133 BIT 7 - 5 Reserved, set to zero. Serial EEPROM Pointer Register, 0xF2 BIT 7 - 0 Use this register to set the Serial EEPROM's pointer. The value in this register always reflects the current EEPROM pointer address. The Serial Device Pointer increments after each pair of reads from the Resource Data register or after each pair of writes to the Program Resource Data register. Write EEPROM Data Register, 0xF3 BIT 7 - 0 This register allows the host to write data into the serial EEPROM. The FDC37C93xAPM supports serial EEPROMS with x16 configurations. Two bytes must be written to this register in order to generate an EEPROM write cycle. The LSB leads the MSB. The first write to this register resets bit 0 of the Write Status register. The second write resets bit 1 of the Write Status register and generates a write cycle to the serial EEPROM. The Write Status register must be polled before performing a pair of writes to this register. Write Status Register, 0xF4 BIT 1 and 0 When = (1,1)Indicates that the Write EEPROM Data register is ready to accept a pair of bytes. When = (1,0) bit 0 is cleared on the first write of the Write EEPROM Data register. This status indicates that the serial device controller has received one byte (LSB) and is waiting for the second byte (MSB). When = (0,0) bit 1 is cleared on the second write of the Write EEPROM Data register indicating that two bytes have been accepted and that the serial device interface is busy writing the word to the EEPROM. BIT 6 - 2 Reserved, set to "0" BIT 7 This bit is cleared to configure the EEPROM interface for Read operations. Clearing this bit enables the serial EEPROM prefetch when the Serial EEPROM Pointer Register is updated (written or auto-incremented). This bit is set to configure the EEPROM interface for Write operations. Setting this bit disables the serial EEPROM prefetch when the Serial EEPROM Pointer Register is updated (written or auto-incremented). Read EEPROM Data Register, 0xF5 BIT 7 - 0 This register allows the host to read data from the serial EEPROM. Data is not valid in this register until bit 0 of the Read Status Register is set. Since the EEPROM is a 16-bit device this register presents the LSB followed by the MSB for each pair of register reads. Immediately after the MSB is read bit-0 of the Read Status Register will be cleared, then the Serial EEPROM Pointer Register will be autoincremented, then the next word of EEPROM data will be fetched, followed by the Read Status Register, bit 0 being set. Read Status Register, 0xF6 Bit[0] When set, indicates that data in the Read EEPROM Data register is valid. This bit is cleared when EEPROM Data is read until the next byte is valid. Reading the Read EEPROM Data register when bit 0 is clear will have no detremental effects; the data will simply be invalid. 134 GATEA20 GATEA20 is an internal signal from the Keyboard controller (Port 21). The FDC37C93xAPM may be configured to drive this signal onto GP25 by programming its GPI/O Configuration Register. See the 8042 Keyboard Controller Section for more information. EITHER EDGE TRIGGERED INTERRUPTS Three GPIOs will allow an interrupt to be generated on either a high-to-low or low-to-high edge transition, instead of one or the other as selected by the polarity bit. These GPIOs, GP42, GP23, GP24, pins 23, 108, 109, respectively, can be used to detect system changes. Note: These pins are enabled as interrupts by selecting the "Either Edge Triggered Interrupt Input x Enable" function through bits[4:3]. Selecting the "Either Edge Triggered Interrupt Input x Enable" function for these GPI/O pins is only applicable if the combined interrupt is enabled (GP42 can be enabled onto either GPINT1 or GPINT2; GP23 and GP24 can be enabled onto GPINT1). Otherwise, selection of this function will produce no function for the pin. In addition, if this function is selected, then the bits that control in/out, polarity and open collector/push-pull will have no effect on the function of the pin. However, the polarity will affect the value of the GP bit. An interrupt occurs if the status bit is set and the interrupt is enabled. The status bits indicate which of these interrupts transitioned. These status bits are located in the MSC_STS register (See ACPI section). These bits are cleared by a writing a 1 to their respective bit locations (writing a 0 has no effect). The status is valid whether the interrupt is enabled or not and whether or not the pin is selected for either edge triggered interrupt. Note: These additional interrupts will go through the same selectable debounce/digital filter circuit as any interrupt that is steered onto one of the GP group interrupts. These interrupts function as follows: when an edge comes in, an interrupt is generated and the status bit is set. When the interrupt is serviced, the status bit is cleared. When the next edge comes in, an interrupt is generated and the status bit is set. Again, when the interrupt is serviced, the status bit is cleared. See Figure 6 below. GPI/O Pin GP Interrupt Cleared by a Write to the Status Bit FIGURE 6 - EITHER EDGE TRIGGERED INTERRUPT TIMING EXAMPLE 135 8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL DESCRIPTION The FDC37C93xAPM is a Ultra I/O, Real Time Clock and Universal Keyboard Controller designed for intelligent keyboard management in desktop computer applications. The Ultra I/O supports a floppy disk controller, two 16550type serial ports, one ECP/EPP parallel port and two IDE drive interfaces with support for four drives. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the FDC37C93xAPM enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook. P24 P25 P21 P20 KIRQ MIRQ GP25 GP20 (WD Timer) 8042A P27 P10 P26 TST0 P23 TST1 P22 P11 LS05 KDAT KCLK MCLK MDAT FIGURE 6 - KEYBOARD AND MOUSE INTERFACE KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ GP25 - Port 21 is GP25's alternate function output and can be used to create a GATEA20 signal from the FDC37C93xAPM. GP20 - This general purpose output can be configured as the 8042 Port 2.0 which is typically used to create a "keyboard reset" signal. The 8042's P20 can be used to optionally reset the Watch Dog Timer. 136 KEYBOARD AND RTC ISA INTERFACE The FDC37C93xAPM ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus, the nIOR, nIOW and the Status register, Input Data register, and Output Data register. Table 53 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. Table 53 - ISA I/O Address Map Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN ISA ADDRESS (NOTE 1) BLOCK FUNCTION 0x70 0x71 (R/W) (R/W) RTC RTC Address Register Data Register Bank 0 is at 70h. Bank 1 and 2 are relocatable via the RTC Mode Register and the Secondary Base Address for RTC Bank 1 and 2 (CR62 and CR63). See Configuration section. ISA ADDRESS 0x60 0x64 nIOW 0 1 0 1 nIOR 1 0 1 0 BLOCK KDATA KDATA KDCTL KDCTL FUNCTION* Keyboard Data Write (C/D=0) Keyboard Data Read Keyboard Command Write (C/D=1) Keyboard Status Read Note*: These registers consist of three separate 8 bit registers: Status, Data/Command Write and Data Read. Keyboard Data Write This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software. Keyboard Command Write This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set. Keyboard Status Read This is an 8 bit read only register. Refer to the description of the Status Register for more information. RTC Address Register Writing to this register sets the CMOS address that will be read or written. 137 RTC Data Register A read of this register will read the contents of the selected CMOS register. A write to this register will write to the selected CMOS register. CPU-to-Host Communication The FDC37C93xAPM CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 54. 8042 INSTRUCTION OUT DBB Table 54 - Host Interface Flags FLAG Set OBF, and, if enabled, the KIRQ output signal goes high Host-to-CPU Communication The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. KIRQ If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the FDC37C93xAPM's CPU has written to the output data register via "OUT DBB,A". If P24 is set to a "0", KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS" has not been executed, KIRQ can be controlled by writing to P24. Writing a "0" to P24 forces KIRQ low; a high forces KIRQ high. MIRQ If "EN FLAGS" has been executed and P25 is set to a "1", IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the FDC37C93xAPM's CPU has read the DBB register. If "EN FLAGS" has not been executed, MIRQ is controlled by P25, Writing a "0" to P25 forces MIRQ low; a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support.) Gate A20 A general purpose P21 can be routed out to the general purpose pin GP25 for use as a software-controlled Gate A20 or user-defined output. 138 EXTERNAL INTERFACE KEYBOARD AND MOUSE Industry-standard PC/AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37C93xAPM provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. The FDC37C93xAPM has four high-drive, opendrain output, bidirectional port pins that can be used for external serial interfaces, such as ISA external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11. Note: External pull-ups may be required. KEYBOARD POWER MANAGEMENT The keyboard provides support for two powersaving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped. Efforts must be made to reduce power wherever possible! Soft Powerdown Mode This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET, then a normal reset sequence is initiated and program execution starts from program memory location 0. Hard Powerdown Mode This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilise. Program execution will resume as above. INTERRUPTS The FDC37C93xAPM provides the two 8042 interrupts, IBF and the Timer/Counter Overflow. MEMORY CONFIGURATIONS The FDC37C93xAPM provides 2K of on-chip ROM and 256 bytes of on-chip RAM. REGISTER DEFINITIONS Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. 139 Host I/F Status Register The Status register is 8 bits wide. Table 55 shows the contents of the Status register. Table 55 - Status Register D4 D3 D2 UD C/D UD D7 UD D6 UD D5 UD D1 IBF D0 OBF Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37C93xAPM CPU. UD Writeable by FDC37C93xAPM CPU. These bits are user-definable. C/D Command Data This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. IBF Input Buffer Full This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the FDC37C93xAPM CPU's nIBF (MIRQ) interrupt if enabled. When the FDC37C93xAPM's CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. OBF Output Buffer Full This flag is set to 1 whenever the FDC37C93xAPM CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset. EXTERNAL CLOCK SIGNAL The FDC37C93xAPM's X1K clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally - and externally - generated reset signals. In powerdown mode, the external clock signal on X1K is not loaded by the chip. The FDC37C93xAPM's X1C clock source must be from a crystal connected across X1C and X2C. Due to the low current internal oscillator circuit, this X1C can not be driven by an external clock signal. DEFAULT RESET CONDITIONS The FDC37C93xAPM has one source of reset, an external reset via the RESET pin. Refer to Table 56 for the effect of each type of reset on the internal registers. 140 DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Table 56 - Resets HARDWARE RESET (RESET) Weak High Weak High Weak High Weak High N/A 00H 80H NC Host I/F Status Reg RTCCNTRL RTCADDR RTCDATA NC NC: No Change N/A: Not Applicable GATEA20 AND KEYBOARD RESET The FDC37C93xAPM provides several options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET, Fast GateA20 and KRESET (via Hardware Speed-up) and Port 92 Fast GateA20 and KRESET. Port 92 Fast GateA20 and Keyboard Reset Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. NAME Location Default Value Attribute Size PORT 92 92h 24h Read/Write 8 bits 141 BIT 7:6 5 4 3 2 1 0 Table 57 - Port 92 Register FUNCTION Reserved. Returns 00 when read. Reserved. Returns a 1 when read. Reserved. Returns a 0 when read. Reserved. Returns a 0 when read. Reserved. Returns a 1 when read. ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high. Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse acitive (low) for a minimum of 1 s after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0. Table 58 - nGATEA20 8042 P21 0 0 1 1 ALT_A20 0 1 0 1 System nA20M 0 1 1 1 Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND'ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6s after a delay of a minimum of 14s. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). The diagram on the following page illustrates the generation of the nALT_RST function. If software control is selected, i.e., bit 0 of KRST_GA20 is set to 0, the reset pulse is generated by the 8042 upon writing an FE command to register 64. If hardware speed-up is selected, i.e., bit 0 of KRST_GA20 is set to 1, the reset pulse is generated in hardware upon writing an FE command to register 64. In addition, if Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is also generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is ANDed with the 142 pulse generated above. This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration. 14us ~ ~ 6us 8042 P20 KRST FE Command MUX Pulse Gen KRST_GA20 Bit 0 KRST_GA20 Bit 2 nALT_RST Bit 0 Pulse Gen 14us GPI/O Polarity Config KRESET P92 Note: When Port 92 is disabled, writes are ignored and reads return undefined values. FIGURE 7 - KRESET GENERATION Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR'ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. The diagram on the following page illustrates the logic for the generation of the Gate A20 signal. ~ ~ 6us 143 GateA20 Logic 64&nAEN KRST_GA20 Bit 1 A nIOW nIOW DD1 nIOW 8042 Address DFF DFE KRST_GA20 Bit 0 nAEN&60 nIOW DD1 After D1 D[1] GA20 A CPURST To KRESET Gen A20GATE MUX GPI/O Polarity Config GateA20 nIOW nAEN&64 nIOW nAEN&60 D Trailing Edge Delay P92 KRST_GA20 Bit 1 KRST_GA20 Bit 2 ALT_A20 Bit 1 VCC A nIOW 24MHz Delay Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Note: Use 64 and 60 or the alternate addresses for command and data ports. FIGURE 8 - GATEA20 GENERATION LOGIC The timing for a D1 command write followed by a data write is shown on the following page. This is the GATEA20 turn-on sequence shown in the Table "GATE20 Command/Data Sequence Examples". 144 0ns 250ns 500ns CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 FIGURE 9 - GATE A20 TURN-ON SEQUENCE TIMING When writing to the command and data port with hardware speedup, the IOW timing shown in the figure titled "IOW Timing for Port 92" in the Timing Diagrams Section is used. This setup time is only required to be met when using hardware speedup; the data must be valid a minimum of 0 nsec from the leading edge of the write and held throughout the entire write cycle. 145 FAST GATEA20 AND KEYBOARD RESET GATEA20/KRESET Hardware Speed-Up The FDC37C93xAPM contains on-chip logic support for the GATEA20 and KRESET hardware speed-up feature. GATEA20 from the chip is part of the control required to mask address line A20 to emulate 8086 addressing. GATEA20 and KRESET is configured via a byte at F0 in the keyboard configuration space, Logical Device 7. The byte is defined below. NAME KRST_GA20 Table 59 - GATEA20/KRESET REG INDEX DESCRIPTION 0xF0 Bits[7:3] Reserved Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] GATEA20 Select = 0 8042 Software Control = 1 Hardware Speed-up Bit[0] KRESET Select = 0 8042 Software Control = 1 Hardware Speed-up STATE C When the chip receives a "D1" command followed by data (via the host interface), the onchip hardware copies the value of data bit 1 in the received data field to the GATEA20 host latch. It also copies the value of D[0] to KRESET latch. At no time during this hostinterface transaction will PCOBF or the IBF flag (bit 1) in the Status register be activated; i.e., this host control of GATEA20 is transparent to firmware, with no consequent degradation of overall system performance. Table 60 details the possible GATEA20 sequences and the chip responses. On VCC1 POR, GATEA20 and KRESET pins will float. GATEA20 comes from either the software control or hardware speed-up and they are mutually exclusive. If Port 92 is enabled, GATEA20 from one of these two are merged along with Port 92. See Port 92 Section. KRESET comes from either the software control or hardware speed-up and they are mutually exclusive. If Port 92 is enabled, KRESET from one of these two are merged along with Port 92. See Port 92 Section. 146 SA2 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 R/W W W W W W W W W W W W W W W W W W Table 60 - GATEA20 Command/Data Sequence Examples IBF D[0:7] FLAG GATEA20 COMMENTS GATEA20 Turn-on Sequence Q 0 D1 1 0 D[1]=1 Q 0 FF GATEA20 Turn-off Sequence Q 0 D1 0 0 D[1]=0 Q 0 FF GATEA20 Turn-on Sequence(*) Q 0 D1 Q 0 D1 1 0 D[1]=1 Q 0 FF GATEA20 Turn-off Sequence(*) Q 0 D1 Q 0 D1 0 0 D[1]=0 Q 0 FF Invalid Sequence Q 0 D1 Q 1 XX** Q 1 FF Notes: "Q" indicates the bit remains set at the previous state. *Not a standard sequence. **XX = Anything except D1. If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual happened. For data bytes SA2=0, only D[1] is used; all other bits are don't care. The polarity control bit for GPI/O controls the polarity of GATEA20. Table 61 below details the possible KRESET sequences and the chip responses. Table 61 - KRESET Command/Data Sequence Examples IBF R/W D[0:7] FLAG COMMENTS W FE 0 Pulse KRESET The polarity control bit for GPI/O controls the polarity of KRESET. SA2 1 When an FE command is received, pulse KRESET. KRESET is pulsed low for a minimum of 6s pulse width after a minimum of a 14s delay. 147 REAL TIME CLOCK The Real Time Clock is a complete time of day clock with two alarms, calendar (up to the year 9999), a programmable periodic interrupt, and a programmable square wave generator. Features RTC Reset The clock, calendar, or RAM functions are not affected by the system reset (RESET_DRV active). When the RESET_DRV pin is active (i.e., system reset) and the battery voltage is above 1 volt nominal, the following occurs: 1. Periodic Interrupt Enable (PIE) is cleared to 0. Alarm Interrupt Enable (AIE) bit is cleared to 0. Update Ended Interrupt Enable (UIE) bit is cleared to 0. Update Ended Interrupt Flag (UF) bit is cleared to 0. Interrupt Request Status Flag (IRQF) bit is cleared to 0. Periodic Interrupt Flag (PIF) is cleared to 0. The RTC and CMOS registers are not accessable. Alarm Interrupt Flag (AF) is cleared to 0. nIRQ pin is in high impedance state. * * * * * * * Counts seconds, minutes, and hours of the day. Counts days of the week, date, month, year and century. Time of Day Alarm Time Of Century Wake-Up Alarm Binary or BCD representation of time, calendar and alarms. Three interrupts - each is separately software maskable. (No daylight savings time!) 256 Bytes of CMOS RAM. 2. 3. 4. 5. 6. 7. 8. 9. Port Definition and Description OSC Crystal Oscillator input. frequency is 32.768 kHz. Maximum clock When RESET_DRV is active and the battery voltage is below 1 volt nominal, the following occurs: 1. 2. Registers 00-0D are initialized to 00h. Access to all registers from the host or FDC37C93xAPM's CPU (8042) are blocked. 148 RTC Interrupt The interrupt generated by the RTC is an active high output. The RTC interrupt output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. Activating RESET_DRV or reading register C clears the RTC interrupt. The RTC Interrupt is brought out by programming the RTC Primary Interrupt Select to a non-zero value. If IRQ 8 is selected then the polarity of this IRQ 8 output is programmable through a bit in the OSC Global Configuration Register. INTERNAL REGISTERS Table 62A shows the address map of the RTC, ten bytes of time, calendar, and alarm 1 data, four control and status bytes and 114 bytes of "CMOS" registers. ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D E-7F Table 62A - Real Time Clock Address Map, Bank 0 REGISTER TYPE REGISTER FUNCTION R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W Register 0: Seconds Register 1: Seconds Alarm 1 Register 2: Minutes Register 3: Minutes Alarm 1 Register 4: Hours Register 5: Hours Alarm 1 Register 6: Day of Week Register 7: Date of Month Register 8: Month Register 9: Year Register A: Register B: (Bit 0 is Read Only) Register C: Register D: Register E-7F: General Purpose All 14 bytes are directly writable and readable by the host with the following exceptions: a. b. c. Registers C and D are read only Bit 7 of Register A is read only Bits 0 of Register B is read only 149 Table 62B shows Bank 1, the second bank of CMOS registers which contains an additional 128 bytes of general purpose CMOS registers. All 128 bytes are directly writeable and readable by the host. ADDRESS 0-7F Table 62B - Real Time Clock Address Map, Bank 1 REGISTER TYPE REGISTER FUNCTION R/W Register 0-7F: General Purpose All 9 bytes are directly writable and readable by the host. Table 62C shows the address map of Bank 2, the third bank of CMOS registers, which contain the registers for the century byte and the second alarm function. ADDRESS 40 41 42 43 44 45 46 47 48 Table 62C - Real Time Clock Address Map, Bank 2 REGISTER TYPE REGISTER FUNCTION R/W R/W R/W R/W R/W R/W R/W R/W R/W Register 0: Century Byte Register 1: Seconds Alarm 2 Register 2: Minutes Alarm 2 Register 3: Hours Alarm 2 Register 4: Day of Week Alarm 2 Register 5: Date of Month Alarm 2 Register 6: Month Alarm 2 Register 7: Year Alarm 2 Register 8: Control Register 1 and seven alarm 2 bytes can also be in binary or BCD as shown in Table 63B. Before initializing the internal registers, the SET bit in Register B should be set to a "1" to prevent time/calendar updates from occurring. The program initializes the ten locations in the binary or BCD format as defined by the DM bit in Register B. The SET bit may now be cleared to allow updates. The 12/24 bit in Register B establishes whether the hour locations represent 1 to 12 or 0 to 23. The 12/24 bit cannot be changed without reinitializing the hour locations. When the 12 Note: One or two of the three banks of CMOS Registers are selected via the RTC Mode Register (Logical Device 6, 0xF0). Banks 1 and 2 are also relocatable via the RTC Mode Register and the Secondary Base Address (CR62 and CR63). See Configuration Section. Time Calendar and Alarm The processor program obtains time and calendar information by reading the appropriate locations. The program may initialize the time, calendar and alarm by writing to these locations. The contents of the ten time, calendar and alarm 1 bytes can be in binary or BCD as shown in Table 63A. The contents of the century byte 150 hour format is selected, the high order bit of the hours byte represents PM when it is a "1". Once per second, the ten time, calendar and alarm 1 bytes as well as the century byte and seven alarm 2 bytes are switched to the update logic to be advanced by one second and to check for an alarm condition. If any of these bytes are read at this time, the data outputs are undefined. The update cycle time is shown in Table 63. The update logic contains circuitry for automatic end-of-month recognition as well as automatic leap year compensation. The three alarm 1 bytes may be used in two ways. First, when the program inserts an alarm time in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second usage is to insert a "don't care" state in one or more of three alarm bytes. The "don't care" code is any hexadecimal byte from C0 to FF inclusive. That is the two most significant bits of each byte, when set to "1" create a "don't care" situation. An alarm interrupt each hour is created with a "don't care" code in the hours alarm location. Similarly, an alarm is generated every minute with "don't care" codes in the hours and minutes alarm bytes. The "don't care" codes in all three alarm bytes create an interrupt every second. 151 ADD 0 1 2 3 4 Table 63A - Time, Calendar and Alarm 1 Bytes REGISTER FUNCTION BCD RANGE Register 0: Seconds Register 1: Seconds Alarm Register 2: Minutes Register 3: Minutes Alarm Register 4: Hours (12 hour mode) (24 hour mode) 00-59 00-59 00-59 00-59 01-12 am 81-92 pm 00-23 01-12 am 81-92 pm 00-23 01-07 01-31 01-12 00-99 BINARY RANGE 00-3B 00-3B 00-3B 00-3B 01-0C 81-8C 00-17 01-0C 81-8C 00-17 01-07 01-1F 01-0C 00-63 5 Register 5: Hours Alarm (12 hour mode) (24 hour mode) 6 7 8 9 Register 6: Day of Week Register 7: Day of Month Register 8: Month Register 9: Year ADDRESS 40h 41h 42h 43h 44h 45h 46h 47h Table 63B - Century Byte and Alarm 2 Bytes DECIMAL REGISTER FUNCTION RANGE BCD RANGE Register 0: Century Byte 0-99 00-99 Register 1: Seconds Alarm 2 0-59 00-59 Register 2: Minutes Alarm 2 0-59 00-59 12-hr 1-12 01-12 AM Register 3: Hours Alarm 2 mode 81-92 PM 24-hr 0-23 00-23 mode Register 4: Day of Week Alarm 2 1-7 01-07 Register 5: Date of Month Alarm 2 1-31 01-31 Register 6: Month Alarm 2 1-12 01-12 Register 7: Year Alarm 2 0-99 00-99 BINARY RANGE 00-63 00-3B 00-3B 01-0C AM 81-8C PM 00-17 01-07 01-1F 01-0C 00-63 Alarm 2 Function Alarm 2 can only be used as a wake-up alarm to turn on power to the system when the system is powered off. There are two bits used to control alarm 2. The alarm 2 wake-up function is enabled via the alarm 2 Enable bit, AL2_EN, in the Soft Power Enable Register 2. The alarm 2 Remember Enable bit, AL2_REM_EN, in the RTC Control Register 1, is used to power-up the 152 system upon return of power if the alarm 2 time has passed during loss of power. These bits function as follows: If VTR is present: AL2_EN controls whether or not alarm 2 is enabled as a wake-up function. If AL2_EN is set and VTR=5V, the nPowerOn pin will go active (low) when the date/time is equal to the alarm 2 date/time and the power supply will turn on the machine. If VTR is not present: AL2_REM_EN controls whether or not Alarm 2 will power-up the system upon the return of VTR, regardless of the value of AL2_EN. If AL2_REM_EN is set and VTR=0 at the date/time that Alarm 2 is set for, the nPowerOn pin will go active (low) as soon as VTR comes back and the machine will powerup. The seven alarm 2 bytes may be used in two ways. First, when the alarm time is written in the appropriate year, month, date, day, hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time on the day of the week, on the date of the month, in the year if the Alarm 2 Enable bit is high. The second usage is to insert a "don't care" state into one or more of the alarm bytes. The "don't care" code is any hexadecimal byte from C0 to FF inclusive. That is, the two most significant bits of each byte, when set to "1" create a "don't care" situation. An alarm is generated each year if the year byte is set to a "don't care" condition. Similarly, an alarm is generated every month with "don't care" codes in the year and month bytes. An alarm is generated on every day of every month of every year with "don't care" codes in the year, month, date of month and day of week bytes. An alarm is generated each hour, every day of the month, every month, every year when the "don't care" code is set in the year, month, date, day and hours alarm byte. An alarm is generated every minute with "don't care" codes in the year, month, date, day, hours and minutes alarm bytes. The "don't care" codes in all seven alarm bytes creates an interrupt every second. As a final example, an alarm is generated every one of a certain day of the week, i.e., every Friday, by specifying the "don't care" code in the year, month and date of month bytes. Update Cycle An update cycle is executed once per second if the SET bit in Register B is clear and the DV0-DV2 divider is not clear. The SET bit in the "1" state permits the program to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring. The primary function of the update cycle is to increment the seconds byte, check for overflow, increment the minutes byte when appropriate and so forth through to the year of the century byte. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "don't care" code is present. The length of an update cycle is shown in Table 58. During the update cycle the time, calendar and alarm bytes are not accessible by the processor program. If the processor reads these locations before the update cycle is complete the output will be undefined. The UIP (update in progress) status bit is set during the interval. When the UIP bit goes high, the update cycle will begin 244 us later. Therefore, if a low is read on the UIP bit the user has at least 244s before time/calendar data will be changed. 153 Table 64 - Update Cycle Time INPUT CLOCK FREQUENCY 32.768 kHz 32.768 kHz UIP BIT 1 0 UPDATE CYCLE TIME 1948 s MINIMUM TIME UPDATE CYCLE 244 s CONTROL AND STATUS REGISTERS, BANK 0 Bank 0 of the RTC has four registers which are accessible to the processor program at all REGISTER A (AH) MSB b7 UIP b6 DV2 b5 DV1 b4 DV0 b3 RS3 b2 RS2 b1 RS1 LSB b0 RS0 times when Bank 0 is enabled, even during the update cycle. UIP The update in progress bit is a status flag that may be monitored by the program. When UIP is a "1" the update cycle is in progress or will soon begin. When UIP is a "0" the update cycle is not in progress and will not be for at least 244us. The time, calendar, and alarm information is fully available to the program when the UIP bit is zero. The UIP bit is a read only bit and is not affected by RESET_DRV. Writing the SET bit in Register B to a "1" inhibits any update cycle and then clears the UIP status bit. The UIP bit is only valid when the RTC is enabled. Refer to Table 64. DV2-0 Three bits are used to permit the program to select various conditions of the 22 stage divider chain. Table 65 shows the allowable combinations. The divider selection bits are also used to reset the divider chain. When the time/calendar is first initialized, the program may start the divider chain at the precise time stored in the registers. When the divider reset is removed the first update begins one-half second later. These three read/write bits are not affected by RESET_DRV. RS3-0 The four rate selection bits select one of 15 taps on the divider chain or disable the divider output. The selected tap determines rate or frequency of the periodic interrupt. The program may enable or disable the interrupt with the PIE bit in Register B. Table 66 lists the periodic interrupt rates and equivalent output frequencies that may be chosen with the RS0-RS3 bits. These four bits are read/write bits which are not affected by RESET_DRV. 154 Table 65 - Divider Selection Bits REGISTER A BITS OSCILLATOR FREQUENCY 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz DV2 0 0 0 0 1 1 DV1 0 0 1 1 0 1 DV0 0 1 0 1 X X MODE Oscillator Disabled Oscillator Disabled Normal Operate Test Test Reset Driver Table 66 - Periodic Interrupt Rates RATE SELECT 32.768 kHz TIME BASE RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PERIOD RATE OF INTERRUPT 0.0 3.90625 ms 7.8125 ms 122.070 us 244.141 us 488.281 us 976.562 us 1.953125 ms 3.90625 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms 256 Hz 128 Hz 8.192 kHz 4.096 kHz 2.048 kHz 1.024 kHz 512 Hz 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz FREQUENCY OF INTERRUPT 155 REGISTER B (BH) MSB b7 SET b6 PIE b5 AIE b4 UIE b3 RES b2 DM2 b1 24/12 LSB b0 DSE SET When the SET bit is a "0", the update functions normally by advancing the counts once per second. When the SET bit is a "1", an update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the middle of initialization. SET is a read/write bit which is not modified by RESET_DRV or any internal functions. PIE The periodic interrupt enable bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the IRQB port to be driven low. The program writes a "1" to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3-RS0 bits in Register A. A zero in PIE blocks IRQB from being initiated by a periodic interrupt, but the periodic flag (PF) is still set at the periodic rate. PIE is not modified by any internal function, but is cleared to "0" by a RESET_DRV. AIE The alarm interrupt enable bit is a read/write bit, which when set to a "1" permits the alarm flag (AF) bit in Register C to assert IRQB. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes (including a "don't care" alarm code of binary 11XXXXXX). When the AIE bit is a "0", the AF bit does not initiate an IRQB signal. The RESET_DRV port clears AIE to "0". The AIE bit is not affected by any internal functions. UIE The update-ended interrupt enable bit is a read/write bit which enables the update-end flag (UF) bit in Register C to assert IRQB. The RESET_DRV port or the SET bit going high clears the UIE bit. RES Reserved - read as "0". DM The data mode bit indicates whether time and calendar updates are to use binary or BCD formats. The DM bit is written by the processor program and may be read by the program, but is not modified by any internal functions or by RESET_DRV. A "1" in DM signifies binary data, while a "0" in DM specifies BCD data. 24/12 The 24/12 control bit establishes the format of the hours byte as either the 24 hour mode if set to a "1", or the 12 hour mode if cleared to a "0". This is a read/write bit which is not affected by RESET_DRV or any internal function. DSE The daylight savings enable bit is read only and is always set to a "0" to indicate that the daylight savings time option is not available. 156 REGISTER C (CH) - READ ONLY REGISTER MSB b7 IRQF b6 PF b5 AF b4 UF b3 0 b2 0 b1 0 LSB b0 0 IRQF The interrupt request flag is set to a "1" when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 Any time the IRQF bit is a "1", the IRQB signal is driven low. All flag bits are cleared after Register C is read or by the RESET_DRV port. PF The periodic interrupt flag is a read-only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. The RS3 -RS0 bits establish the periodic rate. PF is set to a "1" independent of the state of the PIE bit. PF being a "1" sets the IRQF bit and initiates an IRQB signal when PIE is also a "1". The PF bit is cleared by RESET_DRV or by a read of Register C. AF The alarm interrupt flag when set to a "1" indicates that the current time has matched the alarm time. A "1" in AF causes a "1" to appear in IRQF and the IRQB port to go low when the AIE bit is also a "1". A RESET_DRV or a read of Register C clears the AF bit. UF The update-ended interrupt flag bit is set after each update cycle. When the UIE bit is also a "1", the "1" in UF causes the IRQF bit to be set and asserts IRQB. A RESET_DRV or a read of Register C causes UF to be cleared. b3-0 The unused bits of Register C are read as zeros and cannot be written. 157 REGISTER D (DH) READ ONLY REGISTER MSB b7 VRT b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 LSB b0 0 VRT When a "1", this bit indicates that the contents of the RTC are valid. A "0" appears in the VRT bit when the battery voltage is low. The VRT bit is read only bit which can only be set by a read of Register D. Refer to Power Management for the conditions when this bit is reset. The processor program can set the VRT bit when the time and calendar are initialized to indicate that the time is valid. b6:b0 The remaining bits of Register D are read as zeros and cannot be written. Register EH-FFH: General purpose Registers Eh-FFH are general purpose CMOS registers. These registers can be used by the host or 8042 and are fully available during the time update cycle. The contents of these registers are preserved by the battery power. INTERRUPTS The RTC includes three separate fullyautomatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at rates from one-per-second to one-a-day. The periodic interrupt may be selected for rates from half-a-second to 122.070 s. The update ended interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupts are described in greater detail in other sections. The processor program selects which interrupts, if any, it wishes to receive by writing a "1" to the appropriate enable bits in Register B. A "0" in an enable bit prohibits the IRQB port from being asserted due to that interrupt cause. When an interrupt event occurs a flag bit is set to a "1" in Register C. Each of the three interrupt sources have separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bits may be used with or without enabling the corresponding enable bits. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included in Register C to ensure the bits that are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts are held until after the read cycle. If an interrupt flag is already set when the interrupt becomes enabled, the IRQB port is immediately activated, though the interrupt initiating the event may have occurred much earlier. When an interrupt flag bit is set and the corresponding interrupt-enable bit is also set, the IRQB port is driven low. IRQB is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a "1" whenever the IRQB port is being driven low. 158 Control Registers, Bank 2 Bank 2 of the RTC has one control register. CONTROL REGISTER 1 Default is 0; cleared upon Vbat POR. This register is battery backed-up. D3 0 D2 VTR_POR _EN D1 0 D0 AL2_REM _EN D7 0 D6 0 D5 0 D4 0 AL2_REM_EN - One of the two control bits for the Alarm 2 wakeup function; it is the "remember" enable bit for the second alarm. This bit, if set to 1, wil cause the system to power-up upon return of power if the Alarm 2 time has passed during loss of power. It is only applicable when VTR=0. This bit is independent of the other control bit for the Alarm 2 wake-up function, Al2_EN (bit 4 of the Soft Power Enable Register 2) which controls Alarm 2 when VTR=5V. See the Alarm 2 Function Section for more information. The function of Bit 0 is summarized as follows: If AL2_REM_EN is set and VTR=0 at the date/time that Alarm 2 is set for, the nPowerOn pin will go active (low) and the machine will power-up as soon as VTR comes back. VTR POR - The enable bit for VTR POR. If VTR_POR_EN is set, the nPowerOn pin will go active (low) and the machine will power-up as soon as a VTR POR occurs. Frequency Divider The RTC has 22 binary divider stages following the clock input. The output of the divider is a 1 Hz signal to the update-cycle logic. The divider is controlled by the three divider bits (DV3-DV0) in Register A. As shown in Table 65 the divider control bits can select the operating mode or be used to hold the divider chain reset which allows precision setting of the time. When the divider chain is changed from reset to the operating mode, the first update cycle is one-half second later. The divider control bits are also used to facilitate testing of the RTC. Periodic Interrupt Selection The periodic interrupt allows the IRQB port to be triggered from once every 500 ms to once every 122.07 s. As Table 66 shows, the periodic interrupt is selected with the RS0-RS3 bits in Register A. The periodic interrupt is enabled with the PIE bit in Register B. 159 Power Supply Operational Modes Note: See the Operational Description Section for the Power Supply Operational Modes. Power Management The RAMD signal controls all bus inputs to the RTC and RAM (nIOW, nIOR, RESET_DRV). When asserted, it disallows any modification of the RTC and RAM data by the host or 8042. RAMD is asserted whenever: VCC is below 4.0 volts nominal. When the VTR voltage drops below the battery voltage, the RTC switches to battery power. When VTR rises above the battery voltage, the RTC switches back to VTR power. When the VCC voltage drops below 4.0 volts nominal, all inputs are locked out so that the internal registers cannot be modified by the system. This lockout condition continues for 62 msec (min) to 125 msec (max) after the system power has been restored. The 62 msec lockout does not occur under the following conditions: 1. 2. 3. The Divider Chain Controls (bits 6-4) are in any mode but Normal Operation ("010"). The VRT bit is a "0". When battery voltage is below 1 volt nominal and RESET_DRV is a "1". This will also initialize all registers 00-0D to a "00". To minimize power consumption, the oscillator is not operational under the following conditions: 1. 2. The Divider Chain Controls (bits 6-4) are in Oscillator Disabled mode (000, or 001). If VTR and VCC=0 and the battery power is removed and then re-applied (a new battery is installed) the following occurs: a. The oscillator is disabled immediately. b. Initialize all registers 00-0D to a "00" when VCC is applied. If the battery voltage is between 1 volt nominal and 2.4 volt nominal when VCC is applied: 1. Clear VRT bit to "0". Maintain all other RTC bits in the state as before VCC was applied VCC HYSTER BATTERY REGISTER ACCESS <4.0 1 1 N >4.0 0 x Y Hyster=1 implies that VCC <4.0 volts +/-0.25V; Hyster=0 implies that VCC >4.0 volts +/-0.25V. 160 SOFT POWER MANAGEMENT The FDC37C93xAPM employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. This technique allows for software control over powerdown and wakeup events. In low power mode, the chip runs off of the trickle voltage, VTR, which is 5 volts at 2mA maximum. In this mode, the chip is ready to power up from either the power button or from one of a number of wakeup events including pressing a key, touching the mouse or receiving data from one of the UARTs. The alarm can also be set to power up the system at a predetermined time to perform one or more tasks. The implementation of Soft Power Management is illustrated in Figure 11. A high to low transition on the Button input or on any of the enabled wakeup events (SPx) causes the nPowerOn output to go active low which turns on the main power supply. Even if the power supply is completely lost (i.e., VTR is not present) the power supply can still be turned on upon the return of VTR by an alarm 2 event that has already passed (if the alarm 2 remember bit is enabled) or by a VTR power on reset (if the VTR POR bit is enabled). These bits are described in the RTC section. The Button input can be used to turn off the power supply after a debounce delay. The power supply can also be turned off under software control (via a write to register WDT_CTRL with bit 7 set). 161 Soft Power Mangement OFF_EN Button L OFF_DLY nSPOFF VTR_POR_EN VTR POR Button Input ED; PG AL2_REM_EN Alarm 2 Logic Delay2 Logic nSPOFF1 nBINT OFF_DLY Delay1 VTR Flip Flop 1 D Q CLR SP1 ED; L EN1 nSPOFF1 nPowerOn SPx ED; L ENx nSPOFF1 VBAT POR Logic Soft Power Off nSPOFF1 Open Collector Type output PWRBTNOR_EN Override Timer PWRBTNOR_STS A transition on the Button input or on any enabled SPx inputs causes the nPowerOn output to go active low. A low pulse on the Soft Power Off signal causes the nPowerOn bit to float. ED;PG = Edge Detect, Pulse Generator ED;L = Edge Detect and Latch FIGURE 11 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM Note 1: All soft power management functions run off of VTR. When VTR is present, it supplies power to the RTC. When VTR is not present, Vbat supplies power to the RTC and Flip Flop 1. Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine. Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 in the soft power management circuit to come up `on' if an alarm occurred when VTR was not present. This is gated into wakeup circuitry. Refer to the AL2_REM_EN Bit description in the RTC Control Register section for more information. 162 REGISTERS The following registers can be accessed when in configuration mode at Logical Device 8, Registers B0-B3, B8 and F4, and when not in configuration they can be accessed through the Index and Data Register. Soft Power Enable Registers Soft Power Enable Register 1 (Configuration Register B0, Logical Device 8) This register contains the enable bits for the wake-up function of the nPowerOn bit. When enabled, these bits allow their corresponding function to turn on power to the system. Soft Power Enable Register 2 (Configuration Register B1, Logical Device 8) This register contains additional enable bits for the wake-up function of the nPowerOn bit. When enabled, these bits allow their corresponding function to turn on power to the system. It also contains OFF_EN: After power up, this bit defaults to 1, i.e., enabled. This bit allows the software to enable or disable the button control of power off. Soft Power Status Registers Soft Power Status Register 1 (Configuration Register B2, Logical Device 8) This register contains the status for the wake-up events. Note: The status bit gets set if the wakeup event occurs, whether or not it is enabled as a wakeup function by setting the corresponding bit in Soft Power Enable Register 1. However, only the enabled wakeup functions will turn on power to the system. Soft Power Status Register 2 (Configuration Register B3, Logical Device 8) This register contains additional status for the wake-up events. Note: The status bit gets set if the wakeup event occurs, whether or not it is enabled as a wakeup function by setting the corresponding bit in Soft Power Enable Register 2. However, only the enabled wakeup functions will turn on power to the system. Soft Power Control Registers WDT_CTRL (Configuration Register F4, Logical Device 8) This register is used for soft power management and watchdog timer control. Bits[7:5] are for soft power management: SPOFF, Restart_Cnt, Stop_Cnt. Delay 2 Time Set Register (Configuration Register B8, Logical Device 8) This register is used to set Delay 2 to value from 500msec to 32sec. The default value is 500msec. 163 The power button has an override event as required by the ACPI specification. If the user presses the power button for more than four seconds while the system is in the working state, a hardware event is generated and the system will transition to the off state. There are status and enable bits associated with this feature in the PM1_BLK registers. See the ACPI section. This override event utilizes power button logic to determine that the power button (Button_In) has been pressed for more that four seconds. The override enable/disable bit, PWRBTNOR_EN, allows this override function to be turned on/off. If enabled, this override event will result in setting the override status bit, PWRBTNOR_STS (to be cleared by writing a 1 to its bit position - writing a 0 has no effect), clearing the regular button status bit, PWRBTN_STS, and generating an event to be routed into the soft power management logic to turn off the system. The override status bit alerts the system upon power-up that an override event was used to power down the system, and will be used to properly power-up the system. Figure 11 shows the soft power management logic with the override timer path from the button input. The override timer counts while the button is held (in the present implementation this would be when the button input is high) and is cleared upon release of the button. It has a 0.5 second or faster resolution (run off of the 32kHz clock divided down) and the minimum time for triggering the override power down is four seconds, with a maximum of 4.5 seconds. The timer output will pulse the clear on the Flip Flop 1. Figure 12 illustrates the timing of the blanking period relative to Button_In and nPowerOn for the override event. Button_In 4+ nPowerOn 4 sec Blanking Period 4 sec sec Release Vcc FIGURE 12 - BLANKING PERIOD 164 SYSTEM MANAGEMENT INTERRUPT (SMI) The FDC37C93xAPM implements a group nSMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for transparent power management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output is then enabled onto the group nSMI output pin via bit[7] in the SMI Enable Register 2. The logic equation for the nSMI output is as follows: nSMI = (EN_IDE1 and IRQ_IDE1) (EN_PINT and IRQ_PINT) (EN_U2INT and IRQ_U2INT) (EN_U1INT and IRQ_U1INT) (EN_FINT and IRQ_FINT) (EN_GPINT2 and IRQ_GPINT2) (EN_GPINT1 and IRQ_GPINT1) (EN_WDT and IRQ_WDT) (EN_MINT and IRQ_MINT) (EN_KINT and IRQ_KINT) (EN_IRINT and IRQ_IRINT) (EN_BINT and iRQ_BINT) (EN_ABINT and IRQ_ABINT) or or or or or or or or or or or or SMI Enable Registers SMI Enable Register 1 (Configuration Register B4, Logical Device 8) This register is used to enable the different interrupt sources onto the group nSMI output. SMI Enable Register 2 (Configuration Register B5, Logical Device 8) This register is used to enable additional interrupt sources onto the group nSMI output. This register is also used to enable the group nSMI output onto the nSMI GPI/O pin and the routing of 8042 P12 internally to nSMI. SMI Status Registers SMI Status Register 1 (Configuration Register B6, Logical Device 8) This register is used to read the status of the SMI input events. Note: The status bit gets set whether or not the interrupt is enabled onto the group SMI output. SMI Status Register 2 (Configuration Register B7, Logical Device 8) This register is used to read the status of the SMI input events. Note: The status bit gets set whether or not the interrupt is enabled onto the group SMI output. REGISTERS The following registers can be accessed when in configuration mode at Logical Device 8, Registers B4-B7 and when not in configuration they can be accessed through the Index and Data Register. 165 ACCESS.bus The FDC37C93xAPM supports ACCESS.bus. ACCESS.bus is a serial communication protocol between a computer host and its peripheral devices. It provides a simple, uniform and inexpensive way to connect peripheral devices to a single computer port. A single ACCESS.bus on a host can accommodate up to 125 peripheral devices. The ACCESS.bus protocol includes a physical layer based on the I2C serial bus developed by Philips, and several software layers. The software layers include the base protocol, the device driver interface, and several specific device protocols. For a description of the ACCESS.bus protocol, please refer to the ACCESS.bus Specifications Version 2.2, February 1994, available from the ACCESS.bus Industry Group. The ACCESS.bus interface is based on the PDC8584 controller. The registers are mapped into the ISA I/O register space as set by the configuration registers. The addresses for the registers are shown in Table 67. Table 67 - ACCESS.bus Register Addresses ADDRESS* REGISTER Base+0 Control/Status Base+1 Own Address Base+2 Data Base+3 Clock Note 1: Base I/O Range: [0x00:0x0FFC] on 4 byte boundaries REGISTERS The ACCESS.bus interface has four internal register locations. Two of these, Own Address Register S0 and Clock Register S2, are used for initialization of the chip. Normally they are only written once directly after resetting of the chip. The other two registers, the Data Shift Register S0 and the Control/Status Register S1 (which functions as a double register), are used during actual data transmission/reception. Register S0 performs all serial-to-parallel interfacing with the ACCESS.bus. Register S1 contains ACCESS.bus status information required for bus access and or monitoring. ACCESS.bus Control/Status Register S1 The control/status register controls the ACCESS.bus operation and provides status information. This register has separate read and write functions for all bit positions. The writeonly section provides register access control and control over ACCESS.bus signals, while the read-only section provides ACCESS.bus status information. 166 Table 68 - ACCESS.BUS Control/Status Register S1: Control R/W Bit Def Status R/W Bit Def D7 W PIN D7 R PIN D6 W ES0 D6 R 0 D5 W Reserved D5 R STS D4 W Reserved D4 R BER D3 W ENI D3 R LRB D2 W STA D2 R AAS D1 W STO D1 R LAB D0 W ACK D0 R nBB Bit Definitions Register S1 Control Section The write-only section of S1 enables access to registers S0, S0', S1 and S2, and controls ACCESS.bus operation. BIT 7: PIN Pending Interrupt Not. When the PIN bit is written with a logic 1, all status bits are reset to logic 0, with the exception of PIN which is set to 1, and nBB which is not affected. This may serve as a software reset function. BIT 6: ESO Enable Serial Output. ESO enables or disables the serial ACCESS.bus I/O. When ESO is high, ACCESS.bus communication is enabled; communication with serial shift register S0 is enabled and the S1 bus status bits are made available for reading. With ESO = 0, bits ENI, STA, STO and ACK of S1 can be read for test purposes. BITS 5 and 4: Reserved BIT 3: ENI This bit enables the internal interrupt, nINT, which is generated when the PIN bit is active (logic "0"). BITS 2 and 1: STA and STO These bits control the generation of the ACCESS.bus START condition and transmission of slave address and R/nW bit, generation of repeated START condition, and generation of the STOP condition (see Table 69) STA 1 STO 0 1 0 1 0 1 1 0 0 Table 69 - Instruction Table for Serial Bus Control PRESENT MODE FUNCTION OPERATION SLV/REC START Transmit START+address, remain MST/TRM if R/nW=0; go to MST/REC if R/nW=1 MST/TRM REPEAT START Same as for SLV/REC MST/REC; STOP READ; Transmit STOP go to SLV/REC mode; MST/TRM STOP WRITE Note 1 MST DATA CHAINING Send STOP, START and address after last master frame without STOP sent; Note 2 ANY NOP No operation; Note 3 167 Note 1: In master receiver mode, the last byte must be terminated with ACK bit high (`negative acknowledge') Note 2: If both STA and STO are set high simultaneously in master mode, a STOP condition followed by a START condition + address will be generated. This allows `chaining' of transmissions without relinquishing bus control. Note 3: All other STA and STO mode combinations not mentioned in Table 69 are NOPs. BIT 0: ACK This bit must be set normally to logic "1". This causes the ACCESS.bus to send an acknowledge automatically after each byte (this occurs during the ninth clock pulse) . The bit must be reset (to logic 0) when the ACCESS.bus controller is operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a negative acknowledge on the ACCESS.bus, which halts further transmission from the slave device. Register S1 Status Section The read-only section of S1 enables access to ACCESS.bus status information. BIT 7: PIN (Pending Interrupt Not) This bit is a status flag which is used to synchronize serial communication and is set to logic "0" whenever the chip requires servicing. The PIN bit is normally read in polled applications to determine when an ACCESS.bus byte transmission/reception is completed. Each time a serial data transmission is initiated (by setting the STA bit in the same register) the PIN bit will be set to logic "1" automatically (inactive). When acting as transmitter, PIN is also set to logic "1" (inactive) each time S0 is written. In receiver mode, the PIN bit is automatically set to logic "1" each time the data register S0 is read. After transmission or reception of one byte on the ACCESS.bus (9 clock pulses, including acknowledge) the PIN bit will be automatically reset to logic "0" (active) indicating a complete byte transmission/reception. When the PIN bit is subsequently set to logic "1" (inactive), all status bits will be reset to "0" on a BER (bus error) condition. In polled applications, the PIN bit is tested to determine when a serial transmission/reception has been completed. When the ENI bit (bit 4 of write-only section of register S1) is also set to logic 1 the hardware interrupt is enabled. In this case, the PI flag also triggers and internal interrupt (active low) via the nINT output each time PIN is reset to logic "0". When acting as a slave transmitter or slave receiver, while PIN="0", the chip will suspend ACCESS.bus transmission by holding the SCL line low until the PIN bit is set to logic "1" (inactive). This prevents further data from being transmitted or received until the current data byte in S0 has been read (when acting as slave receiver) or the next data byte is written to S0 (when acting as slave transmitter). PIN bit summary: * The PIN bit can be used in polled applications to test when a serial transmission has been completed. When the ENI bit is also set, the PIN flag sets the internal interrupt via the nINT output. Setting the STA bit (start bit) will set PIN="1" (inactive). In transmitter mode, after successful transmission of one byte on the ACCESS.bus the PIN bit will be * * 168 * * * * * automatically reset to logic "0" (active) indicating a complete byte transmission. In transmitter mode, PIN is set to logic "1" (inactive) each time register S0 is written. In receiver mode, PIN is set to logic "0" (inactive) on completion of each received byte. Subsequently, the SCL line will be held low until PIN is set to logic "1". In receiver mode, when register S0 is read, PIN is set to logic "1" (inactive). In slave receiver mode, an ACCESS.bus STOP condition will set PIN="0" (active). PIN= "0" if a bus error (BER) occurs. 2. ADO; when AAS="1" (Addressed as slave condition) the ACCESS.bus controller has been addressed as a slave. Under this condition, this bit becomes the AD0 bit and will be set to logic "1" if the slave address received was the `general call' (00h) address, or logic "0" if it was the ACCESS.bus controller's own slave address. BIT 6: Logic 0 BIT 5: STS When in slave receiver mode, this flag is asserted when an externally generated STOP condition is detected (used only in slave receiver mode). BIT 4: BER Bus error; a misplaced START or STOP condition has been detected. Resets nBB (to logic "1"; inactive), sets PIN= "0" (active). BIT 3: LRB/AD0 Last Received Bit or Address 0 (general call) bit. This status bit serves a dual function, and is valid only while PIN= "0". 1. LRB holds the value of the last received bit over the ACCESS.bus while AAS="0" (not addressed as slave). Normally this will be the value of the slave acknowledgment; thus checking for slave acknowledgment is done via testing of the LRB. BIT 2: AAS Addressed As Slave bit. Valid only when PIN="0". When acting as slave receiver, this flag is set when an incoming address over the ACCESS.bus matches the value in own address register S0' (shifted by one bit) or if the ACCESS.bus `general call' address (00h) has been received (`general call' is indicated when AD0 status bit is also set to logic "1"). BIT 1: LAB Lost Arbitration Bit. This bit is set when, in multi-master operation, arbitration is lost to another master on the ACCESS.bus. Bit 0: nBB Bus Busy bit. This is a read-only flag indicating when the ACCESS.bus is in use. A "0" indicates that the bus is busy and access is not possible. This bit is set/reset (logic "1"/logic "0") by START/STOP conditions. 169 Own Address Register S0' When the chip is addressed as slave, this register must be loaded with the 7-bit ACCESS.bus address to which the chip is to respond. During initialization, the own address register S0' must be written to, regardless whether it is later used. The Addressed As Slave (AAS) bit in status register S1 is set D7 R/W Reserved D6 R/W Slave Address 6 D5 R/W Slave Address 5 D4 R/W Slave Address 4 when this address is received (the value in S0 is compared with the value in S0'). Note that the S0 and S0' registers are offset by one bit; hence, programming the own address register S0' with a value of 55h will result in the value AAh being recognized as the chip's ACCESS.bus slave address. After reset, S0' has default address 00h. D3 R/W Slave Address 3 D2 R/W Slave Address 2 D1 R/W Slave Address 1 D0 R/W Slave Address 0 Data Shift Register S0 Register S0 acts as serial shift register and read buffer interfacing to the ACCESS.bus. All read and write operations to/from the ACCESS.bus are done via this register. ACCESS.bus data is always shifted in or out of shift register S0. In receiver mode the ACCESS.bus data is shifted into the shift register until the acknowledge phase. Further reception of data is inhibited (SCL held low) until the S0 data shift register is read. In the transmitter mode data is transmitted to the ACCESS.bus as soon as it is written to the S0 shift register if the serial I/O is enabled (ESO=1). D3 R/W D2 R/W D1 R/W D0 R/W D7 R/W D6 R/W D5 R/W D4 R/W 170 Clock Register S2 Register S2 controls the selection of the internal chip clock frequency used for the D5 D4 R AB RST RESERVED Default = 00 at hard reset and power on reset. BIT 7: AB_RST ACCESS.bus Reset Bit. D7 D6 ACCESS.bus block. This determines the SCL clock frequency generated by the chip. The selection is made via Bits[2:0] (see Table 70). D3 D2 D1 R/W See Table 70 D0 This bit resets the entire ACCESS.bus block. Not self-clearing, must be written high and then written low. Table 70 - Internal Clock Rates and ACCESS.bus Data Rates in the FDC37C93xAPM ACCESS BUS CLOCK CLOCK DATA NOMINAL NOMINAL MINIMUM REGISTER D[2:0] RATE RATE HIGH LOW HIGH 000 Off 001 12MHz 50kHz 8s 12s 4s 010 14.318 MHz 60kHz 6.7s 10.1s 4s 011 16MHz 67kHz 6s 9s 4s 100 24MHz 100kHz 4s 6s 4s 101 110 171 ADVANCED CONFIGURATION AND POWER INTERFACE The FDC37C93xAPM supports the Advanced Configuration and Power Interface (ACPI) as described in this section. LEGACY/ACPI SELECT CAPABILITY This capability consists of an SMI/SCI switch which is required if the system supports both legacy and ACPI power management models. This is due to the fact that the system software for legacy power management consists of the SMI interrupt handler while for ACPI it consists of the ACPI driver (SCI interrupt handler). This support uses Logical Device A at 0x0A to hold the address pointers to the ACPI power management register block, PM1_BLK, and the Miscellaneous register block, MSC_BLK. These are run-time registers. Contained in the MSC_BLK are SCI enable and status registers which will allow the SMI interrupt events to be enabled as SCI interrupt events. Included in the PM1_BLK is an enable bit to allow the SCI group interrupt to be switched out to SCI interrupt 13 (pin 97, IRQ13) or routed to one of the dedicated interrupts. The software power management events (those that generate an SMI in legacy mode and an SCI in ACPI mode) are controlled by the EN_SMI and SCI_EN bits. For legacy power management, the EN_SMI bit is used; if set, it routes the power management events to the SMI interrupt logic. For ACPI power management, the SCI_EN bit is used; if set, it routes the power management events to the SCI interrupt logic. The SCI enable bit, SCI_EN, is located in the PM1_CNTRL register, bit 0. This bit is used in conjunction with EN_SMI, bit 7 of the SMI enable register 2, to enable either SCI or SMI (or both). The SCI enable and status registers are runtime registers which have the same interrupt event enable and status bits as the SMI registers. The SCI registers are contained in the MSC_BLK. Logical Device A will hold the address pointers to the ACPI power management register block, PM1_BLK, and the Miscellaneous register block, MSC_BLK. The SCI pin is the second alternate function added to pin 97, with the resulting pin having the multiple functions GP11/IRQIN/IRQ13. The configuration register for this pin (0xE1) allows polarity control and selection of open collector for this interrupt. The nSMI output pin is the second alternate function of pin 31 in the FDC37C93xAPM. The SCI interrupt can be routed to any of the dedicated interrupt request pins, IRQ[1,3:15]. The SCI interrupt is active low open collector for all of these IRQ pins. Note that the SCI interrupt is the only one routed to IRQ13 and its polarity and output type is selected through configuration register 0xE1. GLOBAL STATUS AND BIOS STATUS Figure 13 shows the process of generating an interrupt from SMI to SCI and SCI to SMI. This figure shows the bits involved in this process. The GBL_EN, GBL_STS and GBL_RLS bits are located in the PM1_BLK registers. The BIOS_RLS, BIOS_EN and BIOS_STS bits are located in the MISC_BLK registers. These bits are described below. The BIOS_RLS bit is used by the BIOS to raise an event to the ACPI software. GBL_EN and GBL_STS are the corresponding enable and status bits used by ACPI software to control its ability to receive SCI events. Setting BIOS_RLS sets GBL_STS. If GBL_EN is set and BIOS_RLS is set an SCI is raised. BIOS_RLS is 172 set by writing "1" to its bit location; it is cleared by writing a "1" to the GBL_STS bit. Writing a "0" to BIOS_RLS has no effect. Writing a "0" to GBL_STS has no effect. The GBL_RLS bit is used by the ACPI software to raise an event to the BIOS. BIOS_EN and BIOS_STS are the corresponding enable and status bits used by the BIOS to control its ability to receive ACPI events. Setting GBL_RLS sets BIOS_STS. If BIOS_EN is set and GBL_RLS is set an SMI is raised. GBL_RLS is set by writing a "1" to its bit location; it is cleared by writing a "1" to the BIOS_STS bit. Writing a "0" to GBL_RLS has no effect. Writing a "0" to BIOS_STS has no effect. SMI to SCI Clears GBL_STS BIOS_RLS To SCI Logic GBL_EN SCI to SMI Clears BIOS_STS GBL_RLS To SMI Logic BIOS_EN SYMBOL DEFINITION Enable bit. Software writing this bit HIGH or LOW will result in the bit being read as HIGH or LOW. Sticky Status Bit. This bit is set by a hardware signal assertion HIGH. Cleared by software writing a one to its bit position. Latched on trailing edge of write strobe. FIGURE 13 - PROCESS OF GENERATING AN INTERRUPT FROM SMI TO SCI AND SCI TO SMI 173 Bus Master The Bus Master event logic is shown in Figure 14. The BM_RLD and BM_STS bits are located in the PM1_BLK and BM_CNTRL is located in the MSC_BLK. These bits are described below. Setting BM_CNTRL sets BM_STS. If BM_RLD is set and BM_CNTRL is set, an SCI is raised. BM_CNTRL is set by writing a 1 to its bit location; it is cleared by writing a "1" to the BM_STS bit. Writing a "0" to BM_CNTRL has no effect. Writing a "0" to BM_STS has no effect. C lears BM_STS BM_CNTRL SCI BM_RLD FIGURE 14 - BUS MASTER SCI EVENT LOGIC 174 POWER MANAGEMENT TIMER This is a 24-bit free running timer that is required for ACPI compliance. The power management timer provides an accurate time function while the system is in the working state. This feature is a 24-bit counter which runs off of a 3.579545 MHz clock. To allow software to extend the number of bits in the timer, the power management timer generates an SCI interrupt (if enabled) when the last bit of the timer changes from 0 to 1 or 1 to 0. The implementation also includes a timer enable bit and a timer status bit. Three additional registers are used to read the timer value. Figure 15 shows the power management timer functional diagram. TMR_ON_OFF TMR_STS 24-bit Counter 3.5795454MHz 24 TMR_EN TMR_PME TMR_VAL FIGURE 15 - POWER MANAGEMENT TIMER This circuit has an enable/disable bit to turn the timer on/off (TMR_ON_OFF, MSC_EN Register, bit 1). The default of this bit is disabled (off). It also has a status bit, TMR_STS (PM1_STS register, bit 0), which is set when the timer changes from 0 to 1 or 1 to 0 and is cleared by writing a 1 to its bit location (writing a 0 has no effect). In addition, it has a bit (TMR_EN, PM1_EN register, bit 0) to enable the power management event, TMR_PME, as an SCI event. The default of this enable/disable bit is disabled. The three bytes used to read the 24 bit timer value, TMR_VAL, are located in the PM1_TMR register at bits 0-23. Note: Reading the lower byte of the timer value latches the value in the other 2 bytes. Reading any byte other than the lower byte first won't latch the other 2 bytes, and the data read will be the previous latched data. 175 POWER BUTTON OVERRIDE EVENT The power button has an override event as required for ACPI compliance. See the Soft Power Management Section. If the user presses the power button for more than four seconds while the system is in the working state, a hardware event is generated and the system will transition to the off state. There are status and enable bits associated with this feature in the PM1_BLK registers. RTC ALARM The ACPI specification requires that the RTC alarm generate a hardware wake-up event from the sleeping state. The extended RTC alarm 2 event can be enabled as both an SMI and an SCI event. There is a bit in the SMI Enable Register 2 and the SMI Status Register 2 to enable the RTC alarm 2 event as an SMI interrupt and to read its status. The status bit is set when the RTC generates an alarm event and is cleared by writing a "1" to this bit (writing a "0" has no effect). When the RTC generates an alarm event, the RTC_STS bit will be set. If the RTC_EN bit is set, an RTC hardware power management event will be generated. The RTC_EN bit will be located at bit 6 of the SMI Enable Register 2, Logical Device 8, 0xB5. The RTC_STS bit will be located at bit 6 of the SMI Status Register 2, Logical Device 8, 0xB7. For SCI, the RTC_STS and RTC_EN bits are in the PM1_STS and PM1_EN registers. ACPI REGISTER BLOCK DESCRIPTION The ACPI register model consists of a number of fixed register blocks that perform designated functions. A register block consists of a number of registers that perform Status, Enable and Control functions. The ACPI specification deals with events (which have an associated interrupt status and enable bits, and sometimes an associated control function) and control features. The status registers illustrate what defined function is requesting ACPI interrupt services (SCI). Any status bit in the ACPI specification has the following attributes: Status bits are only set through some defined "hardware event". B. Unless otherwise noted, Status bits are cleared by writing a "HIGH" to that bit position and upon VTR POR. Writing a "0" has no effect. C. Status bits only generate interrupts while their associated bits in the enable register are set. D. Function bit positions in the status register have the same bit position in the enable register (there are exceptions to this rule; special status bits have no enables). Note that this implies that if the respective enable bit is reset and the hardware event occurs, the respective status bit is set, however no interrupt is generated until the enable bit is set. This allows software to test the state of the event (by examining the status bit) without necessarily generating an interrupt. There is a special class of status bits that have no respective enable bit; these are called out specifically, and the respective enable bit in the enable register is marked as reserved for these special cases. The enable registers allow the setting of the status bit to generate an interrupt. As a general rule, there is an enable bit in the enable register for every status bit in the status register. The control register provides special controls for the associated event, or special control features that are not associated with an interrupt event. The ordering of a register block is the status registers, followed by enable registers, followed by control registers. A. 176 Table 71A and 71B list the PM1 and MSCregister blocks and the locations of the registers contained in these blocks. All of these new registers are to be powered by VTR. Table 71C shows the block size and range of base addresses for each block. Table 71A - PM1 Register Block REGISTER SIZE ADDRESS PM1_STS 1 8 177 Power Management 1 Register Block (PM1_BLK) The registers in this block are powered by VTR. Power Management 1 Status Register 1 (PM1_STS 1) Register Location: BIT 0 1-3 4 5 6-7 178 Power Management 1 Status Register 2 (PM1_STS 2) Register Location: 179 Power Management 1 Enable Register 1 (PM1_EN 1) Register Location: BIT 0 1-4 5 6-7 Power Management 1 Enable Register 2 (PM1_EN 2) Register Location: BIT 0 1 2 3-7 180 Power Management 1 Control Register 1 (PM1_CNTRL 1) Register Location: BIT 0 1 2 3-7 Power Management 1 Control Register 2 (PM1_CNTRL 2) Register Location: BIT 0 1 2-7 181 Power Management 1 Timer 1 (PM1_TMR 1) Register Location: BIT 0-7 NAME TMR_VAL Power Management 1 Timer 2 (PM1_TMR 2) Register Location: BIT 0-7 NAME TMR_VAL 182 Power Management 1 Timer 3 (PM1_TMR 3) Register Location: BIT 0-7 NAME TMR_VAL Power Management 1 Timer 4 (PM1_TMR 4) Register Location: BIT 0-7 NAME Reserved 183 Miscellaneous Block (MSC_BLK) The registers in this block are powered by VTR. SCI Status Register 1 (SCI_STS1) This register is used to read the status of the SCI inputs. Register Location: BIT 0 1 2 3 4 5 6 7 NAME IDE1 PINT U2INT U1INT FINT GPINT2 GPINT1 WDT SCI Status Register 2 (SCI_STS2) This register is used to read the status of the SCI inputs. Register Location: BIT 0 1 2 NAME MINT KINT IRINT 3 BINT 4 5 6 7 P12 ABINT Reserved Reserved 184 SCI Enable Register 1 (SCI_EN1). This register is used to enable the different interrupt sources onto the group SCI output, and the group SCI output onto an IRQ pin for SCI. Register Location: Default Value: Attribute: Size: BIT 0 1 2 3 4 5 6 7 NAME EN_IDE1 EN_PINT EN_U2INT EN_U1INT EN_FINT EN_GPINT2 EN_GPINT1 EN_WDT SCI Enable Register 2 (SCI_EN2). This register is used to enable the different interrupt sources onto the group SCI output, and the group SCI output onto an IRQ pin for SCI. Register Location: Default Value: Attribute: Size: NAME 0 1 2 3 4 5 6 7 REG INDEX EN_MINT EN_KINT EN_IRINT EN_BINT EN_P12 EN_ABINT Reserved Reserved 185 Miscellaneous Status Register (MSC_STS) Register Location: BIT 0 NAME BIOS_STS 1 VTRP_STS 2 EETI1_STS 3 EETI2_STS 4 EETI3_STS 5-7 Reserved Miscellaneous Enable Register (MSC_EN) Register Location: BIT 0 1 2-7 186 Miscellaneous Control Register (MSC_CNTRL) Register Location: BIT 0 1 2-7 Note: all bits described as "reserved" in writeable registers must be written with the value 0 when the register is written. 187 CONFIGURATION The configuration of the FDC37C93xAPM is very flexible and is based on the configuration architecture implemented in typical Plug-andPlay components. The FDC37C93xAPM is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the FDC37C93xAPM allows the BIOS to assign resources at POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or VCC Power On Reset the FDC37C93xAPM is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the FDC37C93xAPM into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the FDC37C93xAPM is in Configuration Mode. The SYSOPT pin is latched on the falling edge of the RESET_DRV or on VCC Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at power-up. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin which is shared with the nRTS1 signal on pin 148. During reset this pin is a weak active low signal which sinks 30A. Note: All I/O addresses are qualified with AEN. The INDEX and DATA ports are effective only when the chip is in the Configuration State. Table 89 - Configuration Port I/O Address SYSOPT= 0 PORT NAME (Pull-down resistor) SYSOPT= 1 Refer to Note 1 (10K Pull-up resistor) CONFIG PORT (Note 2) 0x03F0 0x0370 INDEX PORT (Note 2) DATA PORT Note 1: Note 2: 0x03F0 INDEX PORT + 1 0x0370 TYPE Write Write Read/Write If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down. The configuration port base address can be relocated through CR26 and CR27. Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0xAA > Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0x55 > 188 CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode Exit Configuration Mode To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. Programming Example To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of a single write of 0x55 data to the CONFIG PORT. Once the initiation key is received correctly the chip enters into the Configuration State (the auto Config ports are enabled). Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: a. Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT b. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT. Note: if accessing the Global Configuration Registers, step (a) is not required. The following is an example of a configuration program in Intel 8086 assembly language. ;--------------------------------------------------. ; ENTER CONFIGURATION MODE | ;--------------------------------------------------' MOV DX,3F0H MOV AX,055H OUT DX,AL ;--------------------------------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;--------------------------------------------------' MOV DX,3F0H MOV AL,07H OUT DX,AL ; Point to LD# Config Reg MOV DX,3F1H MOV AL, 08H OUT DX,AL ; Point to Logical Device 8 ; MOV DX,3F0H MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,3F1H MOV AL,02H OUT DX,AL ; Update CRE0 ;-------------------------------------------------. ; EXIT CONFIGURATION MODE | ;-------------------------------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL 189 Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500s after Vcc POR (see Power-up Timing Diagram) Table 90 - Configuration Registers INDEX 0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26 0x27 0x28 0x2D 0x2E 0x2F 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5 TYPE W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HARD RESET SOFT / VCC POR VTR POR RESET CONFIGURATION REGISTER GLOBAL CONFIGURATION REGISTERS 0x00 0x03 0x00 0x30 0x01 0x00 0x00 0x04 Sysopt=0: 0xF0 Sysopt=1: 0x70 Sysopt=0: 0x03 Sysopt=1: 0x03 0x00 n/a n/a 0x00 0x00 0x03, 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x00 0x00 n/a 0x00 0x30 0x01 0x00 n/a n/a n/a n/a 0x00 n/a n/a n/a 0x00 0x03, 0xF0 0x06 0x02 n/a n/a n/a n/a n/a Config Control Index Address Logical Device Number Device ID - hard wired Device Rev - hard wired Power Control Power Mgmt OSC Configuration Port Address Byte 0 Configuration Port Address Byte 1 Clock Mask Register TEST 1 TEST 2 TEST 3 Activate Primary Base I/O Address Primary Interrupt Select DMA Channel Select FDD Mode Register FDD Option Register FDD Type Register FDD0 FDD1 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 190 Table 90 - Configuration Registers INDEX 0x30 0x60, 0x61 0x62, 0x63 0x70 0xF0 0xF1 0x30 0x60, 0x61 0x62, 0x63 0x70 0xF0 0x30 0x60, 0x61 0x70 0x74 0xF0 0xF1 0x30 0x60, 0x61 0x70 0xF0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HARD RESET SOFT / VCC POR VTR POR RESET CONFIGURATION REGISTER LOGICAL DEVICE 1 CONFIGURATION REGISTERS (IDE1) 0x00 0x01, 0xF0 0x03, 0xF6 0x0E 0x0C 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 0x00 0x00 0x00, 0x00 0x00 0x04 0x3C 0x00 0x00 0x00, 0x00 0x00 0x00 0x00 0x01, 0xF0 0x03, 0xF6 0x0E 0x0C 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 n/a 0x00 0x00, 0x00 0x00 0x04 n/a n/a 0x00 0x00, 0x00 0x00 n/a Activate Primary Base I/O Address Second Base I/O Address Primary Interrupt Select HDCS0 Address Decoder HDCS1 Address Decoder Activate Primary Base I/O Address Second Base I/O Address Primary Interrupt Select IDE2 Mode Register Activate Primary Base I/O Address Primary Interrupt Select DMA Channel Select Parallel Port Mode Register Parallel Port Mode Register 2 Activate Primary Base I/O Address Primary Interrupt Select Serial Port 1 Mode Register LOGICAL DEVICE 2 CONFIGURATION REGISTERS (IDE2) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 191 Table 90 - Configuration Registers INDEX 0x30 0x60, 0x61 0x70 0xF0 0xF1 0xF2 0x30 0x62, 0x63 0x70 0xF0 0xF1 0xF2 0xF3 0xF4 HARD RESET SOFT TYPE / VCC POR VTR POR RESET CONFIGURATION REGISTER LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W bits[6:0] R bit[7] R/W R R R/W R/W R/W R/W R/W R/W 0x00 0x00, 0x00 0x00 0x00 0x02 0x03 0x00 0x00, 0x70 0x00 0x00 0x00 0x00 n/a 0x03 0x00 0x00, 0x00 0x00 n/a n/a n/a 0x00 0x00, 0x70 0x00 n/a n/a 0x00 n/a 0x03 Activate Primary Base I/O Address Primary Interrupt Select Serial Port 2 Mode Register IR Options Register IR Half Duplex Timeout Activate Secondary Base Address for RTC Bank 1 and Bank 2 Primary Interrupt Select Real Time Clock Mode Register Serial EEPROM Mode Register Serial EEPROM Pointer Write EEPROM Data Write Status LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RTC) 0xF5 0xF6 0x30 0x70 0x72 0xF0 0x30 0x60, n/a n/a 0x00 0x00 0x00 0x00 0x00 0x00, 0x00 n/a n/a 0x00 0x00 0x00 n/a 0x00 0x00, Read EEPROM Data Read Status Activate Primary Interrupt Select Second Interrupt Select KRESET and GateA20 Select Activate Primary Base I/O Address LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 192 Table 90 - Configuration Registers INDEX 0x61 0x62, 0x63 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCB 0xCC 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HARD RESET / VCC POR 0x00, 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x80 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 VTR POR SOFT RESET 0x00 0x00, 0x00 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a CONFIGURATION REGISTER Second Base I/O Address Soft Power Enable Register 1 Soft Power Enable Register 2 Soft Power Status Register 1 Soft Power Status Register 2 SMI Enable Register 1 SMI Enable Register 2 SMI Status Register 1 SMI Status Register 2 Delay 2 Time Set Register GP40 GP41 GP42 GP43 GP44 GP45 GP46 GP47 GP50 GP51 GP53 GP54 GP60 GP61 GP62 GP63 GP64 GP65 193 Table 90 - Configuration Registers INDEX 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WNote1 0x00 0x00 0x00 0x00 HARD RESET / VCC POR VTR POR 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 SOFT RESET n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a CONFIGURATION REGISTER GP66 GP67 GP70 GP71 GP72 GP73 GP74 GP75 GP76 GP77 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP_INT2 GP_INT1 GPR_GPW_EN WDT_VAL WDT_CFG WDT_CTRL 194 Table 90 - Configuration Registers INDEX 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0x30 0x60, 0x61 0x70 0x30 0x60, 0x61 (2) 0x62, 0x63 (2) 0x70 Note 1: Note 2 : R/W R/W TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HARD RESET / VCC POR 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00, 0x00 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 VTR POR SOFT RESET n/a n/a n/a n/a n/a n/a 0x00 0x00, 0x00 0x00 0x00 0x00, 0x00 0x00, 0x00 0x00 CONFIGURATION REGISTER GP1 GP2 GP4 GP5 GP6 GP7 Activate Primary Base I/O Address Primary Interrupt Select Activate Primary Base I/O Address PM1_BLK Secondary Base I/O Address MSC_BLK Primary Interrupt Select LOGICAL DEVICE 9 CONFIGURATION REGISTERS (ACCESS.bus) LOGICAL DEVICE A CONFIGURATION REGISTERS (ACPI) This register contains some bits which are read or write only. Registers 60 and 62 are the high byte; 61 and 63 are the low byte. For example to set the primary base address to 1234h, write 12h into 60 and 34h into 61. 195 Chip - Level (Global) Control/Configuration Registers [0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessable only in the Configuration Mode. Table 91 - Chip Level Registers REGISTER ADDRESS 0x00 0x01 Config Control Default = 0x00 on Vcc POR or Reset_Drv Index Address Default = 0x03 on Vcc POR or Reset_Drv 0x03 R/W 0x02 W DESCRIPTION Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit [0]=1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register. Bit[7] = 1 Enable GP1, GP2, WDT_CTRL, GP4, GP5, GP6, GP7, Soft Power and SMI Enable and Status Register access when not in configuration mode = 0 Disable GP1, GP2, WDT_CTRL, GP4, GP5, GP6, GP7, Soft Power and SMI Enable and Status Register access when not in configuration mode (Default) Bit [6:2] Reserved - Writes are ignored, reads return 0. Bits[1:0] Sets GP index register address, used when in Run mode (not in Configuration Mode). = 11 0xEA (Default) = 10 0xE4 = 01 0xE2 = 00 0xE0 C STATE Chip (Global) Control Registers 0x04 - 0x06 Reserved - Writes are ignored, reads return 0. 196 Table 91 - Chip Level Registers REGISTER Logical Device # Default = 0x00 on VCC POR or Reset_Drv Card Level Reserved Device ID Hard wired = 0x30 Device Rev Hard wired = 0x01 Power Control Default = 0x00. on Vcc POR or Reset_Drv hardware signal. 0x22 R/W Bit[0] FDC Power Bit[1] IDE1 Enable Bit[2] IDE2 Enable Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] ACCESS.bus Power Bit[7] Reserved (read as 0) =0 Power off or disabled =1 Power on or enabled Bit[0] FDC Bit[1] IDE1 Bit[2] IDE2 Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6:7] Reserved (read as 0) =0 Intelligent Pwr Mgmt off =1 Intelligent Pwr Mgmt on C 0x21 R A read-only register which provides device revision information. Bits[7:0] = 0x01 when read. C ADDRESS 0x07 R/W DESCRIPTION A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: the Activate command operates only on the selected logical device. STATE C 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Chip Level, SMSC Defined 0x20 R A read-only register which provides identification. Bits[7:0] = 0x30 when read. device C Power Mgmt Default = 0x00. on VCC POR or Reset_Drv hardware signal 0x23 R/W C 197 Table 91 - Chip Level Registers REGISTER OSC Default = 0x04, on VCC POR or Reset_Drv hardware signal. ADDRESS 0x24 R/W DESCRIPTION Bit[0] 24/48 MHz Clock Select (Pin 35) =0 24 MHz (Default) =1 48 MHz Bit [1] PLL Control = 0 PLL is on (backward compatible) = 1 PLL is off Bit[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Bit[5:4] Reserved, set to "0" Bit[6] 16 Bit Address Qualification = 0 12 Bit Address Qualification = 1 16 Bit Address Qualification (Refer to the 16-bit Address Qualification in the SMSC Defined Logical Device Configuration Register, Device 2 section.) Bit[7] IRQ8 Polarity = 0 IRQ8 is active high = 1 IRQ8 is active low Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 See Note 1 C STATE C Chip Level Vendor Defined Configuration Address Byte 0 Default =0xF0 (Sysopt=0) =0x70 (Sysopt=1) on VCC POR or Reset_Drv Configuration Address Byte 1 Default = 0x03 on VCC POR or Reset_Drv Clock Mask Register 0x25 0x26 0x27 Bit[7:0] Configuration Address Bits [15:8] See Note 1 C 0x28 Mask clocks as defined below. 0= Clock On, 1= Clock Masked (pin tri-states) 198 Table 91 - Chip Level Registers REGISTER Default = 0x00 on VCC POR and Hard Reset ADDRESS DESCRIPTION Bit[0] 14.318 MHz Clock Output 1 (Pin 37) Bit[1] 14.318 MHz Clock Output 2 (Pin 38) Bit[2] 14.318 MHz Clock Output 3 (Pin 39) Bit[3] 16 MHz Clock Output (Pin 36) Bit[4] High Speed Clock Out 24/48 MHz (Pin 35) Bit[7:5] Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Test Modes: Reserved for SMSC. Users should not write to this register; may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register; may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register; may produce undesired results. C STATE Chip Level Vendor Defined TEST 1 0x29 -0x2C 0x2D R/W TEST 2 0x2E R/W C TEST 3 Default = 0x00, on VCC POR or Reset_Drv hardware signal 0x2F R/W C Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Write byte 0, then byte 1; writing CR27 changes the base address). The configuration address is only reset to its default address upon a Hard Reset or VCC POR. The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin. This change affects SMSC Mode only. 199 Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The nine logical devices are Floppy, IDE1, IDE2, Parallel, Serial 1 and Serial 2, Real Time Clock, Keyboard Controller, and Auxiliary_I/O. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are: Table 92 - Logical Device Registers LOGICAL DEVICE REGISTER ActivateNote1 Default = 0x00 on VCC POR or Reset_Drv Logical Device Control Logical Device Control Mem Base Addr I/O Base Addr. (see Device Base I/O Address Table) Default = 0x00 on VCC POR or Reset_Drv (0x31-0x37) (0x38-0x3f) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] ADDRESS (0x30) DESCRIPTION Bit[7:1] Reserved, set to "0". Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. =0 Logical device currently selected is inactive. Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 91 for the number of base address registers used by each device. Unused registers will ignore writes and return "0" when read. STATE C C C C C 200 Table 92 - Logical Device Registers LOGICAL DEVICE REGISTER Interrupt Select Defaults : 0x70 = 0x00, on VCC POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) Reserved - not implemented. These register locations ignore writes and return zero when read. Only 0x74 is implemented for FDC, serial port 2 and Parallel port. 0x75 is not implemented and ignores writes and returns "0" when read. Refer to DMA Channel Configuration. Reserved - not implemented. These register locations ignore writes and return "0" when read. Reserved - not implemented. These register locations ignore writes and return "0" when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers) Reserved C C ADDRESS (0x70,072) DESCRIPTION 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible). STATE C DMA Channel Select Default = 0x04 on VCC POR or Reset_Drv 32-Bit Memory Space Configuration Logical Device (0x74,0x75) (0x76-0xA8) (0xA9-0xDF) Logical Device Config. (0xE0-0xFE) C Reserved Note 1: 0xFF C A logical device will be active and powered up according to the following equation: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. 201 LOGICAL DEVICE NUMBER 0x00 Table 93 - I/O Base Address Configuration Register Description BASE I/O RANGE FIXED LOGICAL REGISTER (NOTE 1) BASE OFFSETS DEVICE INDEX FDC 0x60,0x61 [0x100:0x0FF8] +0 : SRA (Note 4) ON 8 BYTE BOUNDARIES +1 : SRB +2 : DOR +3 : TSR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR IDE1 (Note 4) 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES IDE TASK +0 : Data Register (16 bit) +1 : ERRF/WPRE +2 : Sector Count +3 : Sector Number +4 : Cylinder Low +5 : Cylinder High +6 : Head,Drive +7 : Status/Command IDE MISC AT + 0 : Status/Fixed Disk IDE TASK +0 : Data Register (16 bit) +1 : ERRF/WPRE +2 : Sector Count +3 : Sector Number +4 : Cylinder Low +5 : Cylinder High +6 : Head,Drive +7 : Status/Command IDE MISC AT + 0 : Status/Fixed Disk 0x01 0x62,0x63 0x02 IDE2 (Note 4) 0x60,0x61 [0x100:0x0FFF] ON 1 BYTE BOUNDARIES [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 0x62,0x63 [0x100:0x0FFF] ON 1 BYTE BOUNDARIES 202 LOGICAL DEVICE NUMBER 0x03 Table 93 - I/O Base Address Configuration Register Description BASE I/O RANGE FIXED LOGICAL REGISTER (NOTE 1) BASE OFFSETS DEVICE INDEX +0 : Data|ecpAfifo Parallel 0x60,0x61 [0x100:0x0FFC] Port ON 4 BYTE BOUNDARIES +1 : Status +2 : Control (EPP not supported) +3 : EPP Address or +4 : EPP Data 0 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES +5 : EPP Data 1 +6 : EPP Data 2 (all modes supported, EPP is only available when +7 : EPP Data 3 the base address is on an 8- +400h : cfifo|ecpDfifo|tfifo |cnfgA byte boundary) +401h : cnfgB +402h : ecr Serial Port 1 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB|LSB div +1 : IER|MSB div +2 : IIR/FCR +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0: Index Register +1: Data Register +0: Index Register +1: Data Register +0 : Data Register +4 : Command/Status Reg. +0 : GPR +0 : GPW 0x04 0x05 Serial Port 2 0x60,0x61 [0x100:0x0FF8] ON 8 BYTE BOUNDARIES 0x06 RTC n/a 0x62,0x63 0x07 0x08 KYBD Aux. I/O n/a 0x60,0x61 0x62,0x63 Not Relocatable Fixed Base Address: 70,71 [0x100:0xFFE] ON 2 BYTE BOUNDARIES Not Relocatable Fixed Base Address: 60,64 [0x00:0xFFF] ON 1 BYTE BOUNDARIES [0x00:0xFFF] ON 1 BYTE BOUNDARIES 203 LOGICAL DEVICE NUMBER 0x09 Table 93 - I/O Base Address Configuration Register Description BASE I/O RANGE FIXED LOGICAL REGISTER (NOTE 1) BASE OFFSETS DEVICE INDEX Access. 0x60,0x61 [0x00:0x0FFC] +0 : Control/Status Reg Bus ON 4 BYTE BOUNDARIES +1 : Own Address Reg +2 : Data Reg +3 : Clock Register ACPI 0x60,0x61 +0: PM1_STS1 [0x0000:0xFFFF] ON 16 BYTE BOUNDARIES +1: PM1_STS2 +2: PM1_EN1 +3: PM1_EN2 +4: PM1_CNTRL1 +5: PM1_CNTRL2 +6: Reserved +7: Reserved +8: PM1_TMR1 +9: PM1_TMR2 +10: PM 1_TMR3 +11: PM 1_TMR4 +0: SCI_STS1 [0x0000:0xFFFF] ON 8 BYTE BOUNDRIES +1: SCI_STS2 +2: SCI_EN1 +3: SCI_EN2 +4: MSC_STS +5: Reserved +6: MSC_EN +7: MSC_CNTRL 0x0A 0x62,0x63 Note 1: Note 2: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. The IDE/FDC split register, normally found at either 0x3F7 or 0x377 is now an FDC support only register. The IDE logical device will now support only a status register (typically found at 0x3F6 or 0x376). The IDE Decoder operates as follows: nHDCS0# = IDE TASK BASE + [7:0] nHDCS1# = IDE MISC AT BASE + 0 (typically located at 0x3F6 or 0x376) 204 NAME Interrupt Request Level Select 0 Default = 0x00 on VCC POR or Reset_Drv Table 94 - Interrupt Select Configuration Register Description REG INDEX DEFINITION 0x70 (R/W) Bit[3:0] selects which interrupt level is used for Interrupt 0. 0x00=no interrupt selected. 0x01=IRQ1 0x02=Reserved 0x03=IRQ3 * * * 0x0D=Reserved/IRQ13 (Note 1) 0x0E=IRQ14 0x0F=IRQ15 All interrupts are edge high (except ECP/EPP) STATE C Note: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND : for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. for the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. for the RTC by (refer to the RTC section of this spec.) for the KYBD by (refer to the KYBD controller section of this spec.) Note: IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A. Note: IRQ 13 is only valid for SCI, as selected through Logical Device A. Table 95 - DMA Channel Select Configuration Register Description REG INDEX DEFINITION 0x74 (R/W) Bit[2:0] select the DMA Channel. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04-0x07= No DMA active NAME DMA Channel Select STATE C Default = 0x04 on VCC POR or Reset_Drv Note 1: Note 2: A DMA channel is activated by setting the DMA Channel Select register to [0x00-0x03] AND : for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. DMAREQ pins must tri-state if not used/selected by any Logical Device. 205 Note A: Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the IRQ and DACK disabled by the Configuration Registers (active bit or address not valid). a. FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance). Will not respond to the DREQ * Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". * The FDC is in power down (disabled). b. IDE1 and IDE2: No additional conditions. c. Serial Port 1 and 2: * Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled. d. Parallel Port: * SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ disabled (high impedance). * ECP Mode: (1) (DMA) dmaEn from ecr register. See table. (2) IRQ - See table. MODE (FROM ECR REGISTER) 000 001 010 011 100 101 110 111 PRINTER SPP FIFO ECP EPP RES TEST CONFIG IRQ PIN PDREQ PIN CONTROLLED BY CONTROLLED BY IRQE IRQE (on) (on) IRQE IRQE (on) IRQE dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn is e. Game Port and ADDR: no IRQ or DACK used. f. Real Time Clock and Keyboard Controller: Refer to the RTC and KBD section of this spec. 206 SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by VCC or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets. Table 96 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME FDD Mode Register Default = 0x0E on VCC POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] Floppy Mode = 0 Normal Floppy Mode (default) = 1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode =0 Burst Mode is enabled =1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] Swap Drives 0,1 Mode =0 No swap (default) =1 Drive and Motor sel 0 and 1 are swapped. Bit[7:5] Reserved, set to zero. Bit[1:0] Reserved, set to zero Bit[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[4] Media ID 0 Polarity = 0: Don't invert (default) = 1: Invert Bit[5] Media ID 1 Polarity = 0: Don't invert (default) = 1: Invert Bits[7:6] Boot Floppy = 00 FDD 0 (default) = 01 FDD 1 = 10 Reserved (neither drive A or B is a boot drive). = 11 Reserved (neither drive A or B is a boot drive). STATE C FDD Option Register Default = 0x00 on VCC POR or Reset_Drv 0xF1 R/W C 207 Table 96 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME FDD Type Register Default = 0xFF on VCC POR or Reset_Drv REG INDEX 0xF2 R/W DEFINITION Bit[1:0] Floppy Drive A Type Bit[3:2] Floppy Drive B Type Bit[5:4] Reserved (could be used to store Floppy Drive C type) Bit[7:6] Reserved (could be used to store Floppy Drive D type) Note: The FDC37C93xAPM supports two floppy drives Reserved, Read as 0 (read only) Bit[1:0] Drive Type Select: DT1, DT0 Bit[2] Read as 0 (read only) Bit[4:3] Data Rate Table Select: DRT1, DRT0 Bit[5] Read as 0 (read only) Bit[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bit[7] Read as 0 (read only) Refer to definition and default for 0xF4 STATE C 0xF3 R FDD0 Default = 0x00 on VCC POR or Reset_Drv 0xF4 R/W C C FDD1 0xF5 R/W C 208 Table 97 - IDE Drive 1, Logical Device 1 [Logical Device Number = 0x01] NAME REG INDEX DEFINITION HDCS0 Address Decoder Default = 0x0C on Vcc POR or Reset_Drv or Software Reset 0xF0 R/W Bit[7:5] Reserved Bit[4:2] Mask Bits 4 3 2 Description 0 0 0 mask no bits (1 byte) 0 0 1 mask lowest bit (2 bytes) 0 1 0 mask lowest 2 bits (4 bytes) 0 1 1 mask lowest 3 bits (8 bytes) 1 0 0 mask lowest 4 bits (16 bytes) 1 0 1 mask lowest 5 bits (32 bytes) 1 1 0 reserved (do not program) 1 1 1 reserved ( do not program) Bit[1:0] Qualify for HDCS0 Option Select 1 0 Description 0 0 = decoded with AEN 0 1 = decoded with AEN and nIOR 1 0 = decoded with AEN and nIOW 1 1 = decoded with AEN and (nIOR or nIOW) HDCS1 Address Decoder Default = 0x00 on Vcc POR or Reset_Drv or Software Reset 0xF1 R/W Bit[7:5] Reserved Bit[4:2] Mask Bits 4 3 2 Description 0 0 0 mask no bits (1 byte) 0 0 1 mask lowest bit (2 bytes) 0 1 0 mask lowest 2 bits (4 bytes) 0 1 1 mask lowest 3 bits (8 bytes) 1 0 0 mask lowest 4 bits (16 bytes) 1 0 1 mask lowest 5 bits (32 bytes) 1 1 0 reserved (do not program) 1 1 1 reserved ( do not program) Bit[1:0] Qualify for HDCS1 Option Select 1 0 Description 0 0 = decoded with AEN 0 1 = decoded with AEN and nIOR 1 0 = decoded with AEN and nIOW 1 1 = decoded with AEN and (nIOR or nIOW) Note: IDE1 HI and LO byte pass through external buffers controlled by IDE1_OE. STATE 209 Table 98 - IDE Drive 2, Logical Device 2 [Logical Device Number = 0x02] NAME IDE2 Mode Register REG INDEX 0xF0 R/W DEFINITION Bit[0] : IDE2 Configuration Options = 0 : IDE2 HI and LO bytes pass through external buffers controlled by IDE2_OE. = 1 : IDE2_OE not used. IDE2 HI and LO byte passes through external buffer controlled by IDE1_OE. Bit[7:1] : Reserved, set to "0" STATE C Default = 0x00 on VCC POR or Reset_Drv When IDE2 is not active (IDE2 active bit = L2 - CR30 - bit 0), nHDCS2, nHDCS3 and IDE2_IRQ are in high impedance; 16_ADR = CR24.6 Table 99 - 16 Bit Address Qualification IDE2 ACTIVE BIT = 1 IDE2 ACTIVE BIT = 0 16BIT_ADR = X 16BIT_ADR = 0 nHDCS2 (pin 27) nHDCS3 (pin 28) IDE2_IRQ (pin 29) nCS (pin 53) Output Output Input (IRQ) Input (SA12) Hi-Z Hi-Z Hi-Z Input (SA12) IDE2 ACTIVE BIT = 0 16BIT_ADR = 1 Input (SA13) Input (SA14) Input (SA15) Input (SA12) 210 Table 100 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME PP Mode Register Default = 0x3C on VCC POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-Directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). = 1 Pulsed Low, released to high-Z. = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. Bit[1:0] PPFDC - muxed PP/FDC control = 00 Normal Parallel Port Mode = 01 PPFD1: Drive 0 is on the FDC pins Drive 1 is on the parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins = 10 PPFD2: Drive 0 is on the parallel port pins Drive 1 is on the Parallel port pins Drive 2 is on the FDC pins Drive 3 is on the FDC pins Bit[7:2] Reserved. Set to "0" STATE C PP Mode Register 2 Default = 0x00 on VCC POR or Reset_Drv 0xF1 R/W 211 Table 101 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME Serial Port 1 Mode Register Default = 0x00 on VCC POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note below STATE C Note: To properly share an IRQ: 1. Configure UART1 (or UART2) to use the desired IRQ pin. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. If both UARTs are configured to use different IRQ pins and the share IRQ bit is set, UART IRQ pins will assert when either UART generates an interrupt. then both of the Table 102 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME Serial Port 2 Mode Register Default = 0x00 on VCC POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed disabled(default) = 1 High Speed enabled Bit[7:2] Reserved, set to "0" STATE C 212 Table 102 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME IR Option Register Default = 0x02 on VCC POR or Reset_Drv REG INDEX 0xF1 R/W DEFINITION Bit[0] Receive Polarity =0 Active High (Default) =1 Active Low Bit[1] Transmit Polarity = 0 Active High = 1 Active Low (Default) Bit[2] Duplex Select =0 Full Duplex (Default) = 1 Half Duplex Bit[5:3] IR Mode = 000 Standard (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux =0 Use Serial port TX2 and RX2 (Default) =1 Use alternate IRRX (pin 98) and IRTX (pin 99) Bit[7] Reserved, write 0. Bit [7:0] These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100sec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100sec STATE C IR Half Duplex Timeout Default = 0x03 on VCC POR or Reset_Drv 0xF2 213 Table 103 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME RTC Mode Register Default = 0x00 on VCC POR or Reset_Drv REG INDEX 0xF0 R/W DEFINITION Bit[0] = 1 Lock CMOS RAM 80-9Fh Bit[1] = 1 Lock CMOS RAM A0-BFh Bit[2] = 1 Lock CMOS RAM C0-DFh Bit[3] = 1 Lock CMOS RAM E0-FFh Bit[6:4] Bank Selection if Bit[7]=1 (Note 1) =000 Bank 1 at Secondary Base Address (Default) (Note 2) =001 Bank 0 at 70h and Bank 1 at Secondary Base Address (Note 3) =010 Reserved (Note 2) =011 Bank 0 at 70h =100 Reserved (Note 2) =101 Bank 0 at 70h =110 Bank 2 at Secondary Base Address (Note 2) =111 Bank 0 at 70h and Bank 2 at Secondary Base Address (Note 3) Bit[7] Bank Selection (Note 1) = 0 Select Bank 0 at 70h = 1 Select Bank(s) based on Bits[6:4] Once set, bit[3:0] cannot be cleared by a write; bit[3:0] are cleared only on VCC Power On Reset or upon a Hard Reset. Bit[0] = 1 : Lock EEPROM 00-1Fh Bit[1] = 1 : Lock EEPROM 20-3Fh Bit[2] = 1 : Lock EEPROM 40-5Fh Bit[3] = 1 : Lock EEPROM 60-7Fh Bit[4] EEPROM Type = 0 256 bit,1 Kbps (93C06,93C46) = 1 2 Kbps, 4 Kbps (93C56,93C66) Bit[7:5] Reserved, set to zero Once set, bit[3:0] can not be cleared by a write; bit[3:0] are cleared only on VCC Power On Reset or upon a Hard Reset. Use this register to set the Serial EEPROM's pointer. The value in this register always reflects the current EEPROM pointer address. The Serial Device Pointer increments after each pair of reads from the Resource Data register or after each pair of writes to the Program Resource Data register. STATE C Serial EEPROM Mode Register Default = 0x00 on VCC POR or Reset_Drv 0xF1 R/W C Serial EEPROM Pointer Default = 0x00, on VCC POR,Reset_Drv or Software Reset. 0xF2 R/W C 214 Table 103 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME Write EEPROM Data REG INDEX 0xF3 W DEFINITION This register is used to program the serial device from the host. This device supports serial EEPROMS in x16 configurations. Two bytes must be written to this register in order to generate an EEPROM write cycle. The LSB leads the MSB. The first write to this register resets bit 0 of the Write Status register. The second write resets bit 1 of the Write Status register and generates a write cycle to the serial EEPROM. The Write Status register must be polled before performing a pair of writes to this register. Bit [1:0] = 1,1 Indicates that the Write EEPROM Data register is ready to accept a pair of bytes. = 1,0 Bit 0 is cleared on the first write of the Write EEPROM Data register. This status indicates that the serial device controller has received one byte (LSB) and is waiting for the second byte (MSB). = 0,0 Bit 1 is cleared on the second write of the Write EEPROM Data register indicating that two bytes have been accepted and that the serial device interface is busy writing the word to the EEPROM. Bit [6:2] Reserved, set to "0" Bit [7] = 0 Enables a prefetch of serial EEPROM when the Serial EEPROM Pointer Register is written. This will typically be used when the host CPU wishes random read access from the serial EEPROM. = 1 Disables a prefetch of serial EEPROM when the Serial EEPROM Pointer Register is written. This bit is typically set when the host CPU wishes to perform random word or block writes to the serial EEPROM. STATE C Write Status Default = 0x03, on VCC POR, Reset_Drv or Software Reset 0xF4 Bit[6:0] Read Only Bit[7] R/W C 215 Table 103 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME Read EEPROM Data REG INDEX 0xF5 R DEFINITION This register allows the host to read data from the serial EEPROM. Data is not valid in this register until bit 0 of the Read Status Register is set. Since the EEPROM is a 16-bit device, this register presents the LSB followed by the MSB for each pair of register reads. Immediately after the MSB is read, bit 0 of the Read Status Register will be cleared, then the Serial EEPROM Pointer Register will be autoincremented, then the next word of EEPROM data will be fetched, followed by the Read Status Register, bit 0 being set. Bit 0 = 1 indicates that data in the Read EEPROM Data register is valid. This bit is cleared when EEPROM Data is read until the next byte is valid. Reading the Read EEPROM Data register when bit-0 is clear will have no detremental effects; the data will simply be invalid. STATE C Read Status 0xF6 R C Note 1: The RTC modifications allow for backwards compatibility. If Bit[7] of the RTC Mode Register is set to 0, Bank 0 is selected at 70h. If Bit[7] is set to 1, the default values for Bit[6:4] and the Secondary Base Address for RTC Bank 1 and 2 (CR62 and CR63) are such that Bank 1 is selected at 70h. For added capability, Banks 1 and 2 can be selected and relocated to another address. Bank 1 can be selected either individually or with Bank 0 by setting Bit[7] of the RTC Mode Register and setting Bit[6:4] appropriately. For example, with Bit[7] = 1, setting Bit[6:4] to 000 selects Bank 1; setting Bit[6:4] to 001 selects Bank 0 and Bank 1. Similarly, Bank 2 can be selected either individually or with Bank 0. For example, with Bit[7] = 1, setting Bit[6:4] to 110 selects Bank 2; setting Bit[6:4] to 111 selects Bank 0 and Bank 2. These banks are relocatable through Configuration Registers 62 and 63 in Logical Device 6, the Secondary Base Address for RTC Bank 1 and Bank 2. This 16-bit address register only applies to Banks 1 and 2 and will only be used for address decode if Bit[7] in the RTC Mode Register is set to 1. As an example, setting CR62 to 04 and CR63 to 70 moves Banks 1 and 2 to address 470h. Bank 0 is always located at 70h. The Secondary Base Address must be at an even address. The Data Register is at the Secondary Base Address + 1. Note 2: Bank 0 is "off" Note 3: The secondary base address must be set to a value other than 70h prior to selecting this option. 216 Table 104 - KEYBOARD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX DEFINITION KRST_GA20 Default = 0x00 on VCC POR or Reset_Drv 0xF0 R/W KRESET and GateA20 Select Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bit[6:3] Reserved Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] GATEA20 Select = 0 Software Control = 1 Hardware Speed-up Bit[0] KRESET Select = 0 Software Control = 1 Hardware Speed-up Reserved - read as "0" STATE 0xF1 0xFF 217 Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG DEFINITION INDEX 0xB0 R/W The following bits are the enables for the wake-up Soft Power Enable function of the nPowerOn bit. When enabled, these Register 1 bits allow their corresponding function to turn on power to the system. Default = 0x00 on VTR POR 1 = ENABLED 0 = DISABLED Bit[0] SP_RI1: UART 1 Ring Indicator Pin Bit[1] SP_RI2: UART 2 Ring Indicator Pin Bit[2] SP_KCLK: Keyboard Clock pin Bit[3] SP_MCLK: Mouse Clock pin Bit[4] SP_GPINT1: Group Interrupt 1 Bit[5] SP_GPINT2: Group Interrupt 2 Bit[6] SP_IRRX2: IRRX2 input pin Bit[7] SP_RTC ALARM: RTC Alarm Soft Power Enable 0xB1 R/W The following bits are the enables for the wake-up Register 2 function of the nPowerOn bit. When enabled, these bits allow their corresponding function to turn on power to the system. Default = 0x80 on VTR POR 1 = ENABLED 0 = DISABLED Bit[0] SP_RXD1: UART 1 Receive Data Pin Bit[1] SP_RXD2: UART 2 Receive Data Pin Bit[3:2] Reserved Bit[4] AL2_EN: Alarm 2 Enable. Defaults to 0. Bit[5] Reserved Bit[6] PG_EN: Power Good Enable. Defaults to 0. =0 Disabled (nPowerOn pin not used for power good) =1 Enabled (nPowerOn pin used as power good) Bit[7] OFF_EN: After power up, this bit defaults to 1, i.e., enabled. This bit allows the software to enable or disable the button control of power off. STATE C C 218 Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG DEFINITION INDEX 0xB2 R/W The following bits are the status for the wake-up Soft Power Status function of the nPowerOn bit. These indicate which of Register 1 the enabled wakeup functions caused the power up. Default = 0x00 1 = Occured on VTR POR 0 = Did not occur since last cleared The following signals are latched to detect and hold the soft power event (Type 1) Bit[0] RI1: UART 1 Ring Indicator; high to low transition on the pin, cleared by a read of this register Bit[1] RI2: UART 2 Ring Indicator; high to low transition on the pin, cleared by a read of this register Bit[2] KCLK: Keyboard clock; high to low transition on the pin, cleared by a read of this register Bit[3] MCLK: Mouse clock; high to low transition on the pin, cleared by a read of this register Bit[6] IRRX2: IRRX2 input; high to low transition on the pin, cleared by a read of this register Bit[7] RTC ALARM: RTC Alarm; status of the RTC Alarm internal signal. Cleared by a read of the status register. The following signals are not latched to detect and hold the soft power event (Type 2) Bit[4] GPINT1: Group Interrupt 1; status of the GPINT1 internal signal. Cleared at the source. Bit[5] GPINT2: Group Interrupt 2; status of the GPINT2 internal signal. Cleared at the source. STATE C 219 Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG DEFINITION INDEX 0xB3 R/W The following bits are the status for the wake-up Soft Power Status function of the nPowerOn bit. These indicate which Register 2 of the enabled wakeup functions caused the power up. Default = 0x00 on VTR POR 1 = Occured 0 = Did not occur since last cleared The following signals are latched to detect and hold the soft power event (Type 1) Bit[0] RXD1: UART 1 Receive Data; high to low transition on the pin, cleared by a read of this register Bit[1] RXD2: UART 2 Receive Data; high to low transition on the pin, cleared by a read of this register Bit[4] AL2: RTC Alarm 2 status; Cleared by a read of this register. Bit[5] Reserved The following signal is latched to detect and hold the soft power event (Type 3) but the output of the latch does not feed into the power down circuitry: Bit[2] Button: Button pressed, Cleared by a read of this register Bit[3] Reserved Bits[7:6] Reserved This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] EN_IDE1 Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] EN_GPINT2 Bit[6] EN_GPINT1 Bit[7] EN_WDT STATE C SMI Enable Register 1 Default = 0x00 on VTR POR 0xB4 R/W C 220 Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG DEFINITION INDEX 0xB5 R/W This register is used to enable the different interrupt SMI Enable sources onto the group nSMI output, and the group Register 2 nSMI output onto the nSMI GPI/O pin. Default = 0x00 Unless otherwise noted, on VTR POR 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_IRINT Bit[3] EN_BINT Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI. 0=Do not route to nSMI, 1=Enable routing to nSMI. Bit[5] EN_ABINT: Access bus interrupt. Bit[6] RTC_EN: This bit is used to enable the setting of the RTC_STS bit to generate an SMI. The RTC_STS bit is set anytime the RTC generates an alarm 2. Bit[7] EN_SMI: Enable the group nSMI output onto the nSMI GPI/O pin. 0=SMI pin floats, 1=Enable group nSMI output onto nSMI GPI/O pin. This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] IDE1 (IDEInterrupt) Bit[1] PINT (Parallel Port Interrupt) Bit[2] U2INT (UART 2 Interrupt) Bit[3] U1INT (UART 1 Interrupt) Bit[4] FINT (Floppy Disk Controller Interrupt) Bit[5] GPINT2 (Group Interrupt 2) Bit[6] GPINT1 (Group Interrupt 1) Bit[7] WDT (Watch Dog Timer) STATE C SMI Status Register 1 Default = 0x00 on VTR POR 0xB6 R/W C 221 Table 105 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG DEFINITION INDEX 0xB7 R/W This register is used to read the status of the SMI SMI Status inputs. Register 2 Bit[0] MINT: Mouse Interrupt. Cleared at source. Bit[1] KINT: Keyboard Interrupt. Cleared at source. Default = 0x00 Bit[2] IRINT: This bit is set by a transition on the IR on VTR POR pin (RDX2 or GP12 as selected in CR L5-F1-B6 i.e., after the MUX). Cleared by a read of this register. Bit[3] BINT: This bit is set when the DELAY counter is started. Cleared by a read of this register. Bit[4] P12: 8042 P1.2. Cleared at source Bit[5] ABINT: Access Bus Interrupt. Cleared at source. Bit[6] RTC_STS: This bit is set when the RTC generates an alarm 2. Additionally if the RTC_EN bit is set then the setting of the RTC_STS bit will generate an SMI. Cleared by writing a 1 to this location. Writing a 0 has no effect. Bit[7] Reserved Delay 2 Time Set 0xB8 R/W This register is used to set Delay 2 (for Soft Power Register Management) to a value from 500 msec to 32 sec. The default value is 500msec. Default = 0x00 on VTR POR Bit[5:0] The value of these bits correspond to the delay time as follows: 000000= 500msec min to 510msec max 000001= 1sec min to 1.01sec max 000010= 1.5sec min to 1.51sec max 000011= 2sec min to 2.01sec max ... 111111 = 32sec min to 32.01sec max Bit[7:6] Reserved STATE C C 222 Table 105 (cont'd) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE C GP40 0xC0 General Purpose I/O bit 4.0 Bit[4:3] Function Select =00 MEDIA_ID1 Default= 0x01 =01 GPI/O on VTR POR =10 IR Mode =11 IRR3 C GP41 0xC1 General Purpose I/O bit 4.1 Bit[4:3] Function Select =00 MEDIA_ID0 Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved C GP42 0xC2 General Purpose I/O bit 4.2 Bit[4:3] Function Select =00 nIDE1_OE Default= 0x00 =01 GPI/O on VTR POR =10 Either Edge Triggered Interrupt Input 1 Enable =11 Reserved GP43 0xC3 General Purpose I/O bit 4.3 C Bit[4:3] Function Select Default= 0x00 =00 nHDCS0 on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP44 0xC4 General Purpose I/O bit 4.4 C Bit[4:3] Function Select Default= 0x00 =00 nHDCS1 on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP45 0xC5 General Purpose I/O bit 4.5 C Bit[4:3] Function Select Default= 0x01 =00 IDE1_IRQ on VTR POR =01 GPI =10 Reserved =11 Reserved 223 Table 105 (cont'd) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE C GP46 0xC6 General Purpose I/O bit 4.6 Bit[4:3] Function Select =00 nIOROP Default= 0x01 =01 GPI/O on VTR POR =10 Power LED Output =11 WDT C GP47 0xC7 General Purpose I/O bit 4.7 Bit[4:3] Function Select =00 nIOWOP Default= 0x01 =01 GPI/O on VTR POR =10 nSMI =11 Reserved C GP50 0xC8 General Purpose I/O bit 5.0 Bit[4:3] Function Select =00 Button_In Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved GP51 0xC9 General Purpose I/O bit 5.1 C Bit[4:3] Function Select Default= 0x80 =00 nPowerOn on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP53 0xCB General Purpose I/O bit 5.3 C Bit[4:3] Function Select Default= 0x01 =00 nROMCS on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP54 0xCC General Purpose I/O bit 5.4 C Bit[4:3] Function Select Default= 0x01 =00 nROMOE on VTR POR =01 GPI/O =10 IR Mode =11 IRR3 0xCD-0xCF Reserved C GP60 0xD0 General Purpose I/O bit 6.0 C Bit[4:3] Function Select Default= 0x01 =00 RD0 on VTR POR =01 GPI/O =10 Power Led Output =11 Reserved 224 Table 105 (cont'd) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE C GP61 0xD1 General Purpose I/O bit 6.1 Bit[4:3] Function Select =00 RD1 Default= 0x01 =01 GPI/O on VTR POR =10 WDT =11 Reserved C GP62 0xD2 General Purpose I/O bit 6.2 Bit[4:3] Function Select =00 RD2 Default= 0x01 =01 GPI/O on VTR POR =10 8042 - P12 =11 Reserved C GP63 0xD3 General Purpose I/O bit 6.3 Bit[4:3] Function Select =00 RD3 Default= 0x01 =01 GPI/O on VTR POR =10 8042 - P13 =11 Reserved GP64 0xD4 General Purpose I/O bit 6.4 C Bit[4:3] Function Select Default= 0x01 =00 RD4 on VTR POR =01 GPI/O =10 8042 - P14 =11 Reserved GP65 0xD5 General Purpose I/O bit 6.5 C Bit[4:3] Function Select Default= 0x01 =00 RD5 on VTR POR =01 GPI/O =10 8042 - P15 =11 Reserved GP66 0xD6 General Purpose I/O bit 6.6 C Bit[4:3] Function Select Default= 0x01 =00 RD6 on VTR POR =01 GPI/O =10 8042 - P16 =11 Reserved GP67 0xD7 General Purpose I/O bit 6.7 C Bit[4:3] Function Select Default= 0x01 =00 RD7 on VTR POR =01 GPI/O =10 8042 - P17 =11 Reserved 225 Table 105 (cont'd) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE C GP70 0xD8 General Purpose I/O bit 7.0 Bit[4:3] Function Select =00 nRI2 Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved C GP71 0xD9 General Purpose I/O bit 7.1 Bit[4:3] Function Select =00 nDCD2 Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved C GP72 0xDA General Purpose I/O bit 7.2 Bit[4:3] Function Select =00 RXD2 Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved GP73 0xDB General Purpose I/O bit 7.3 C Bit[4:3] Function Select Default= 0x01 =00 TXD2 on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP74 0xDC General Purpose I/O bit 7.4 C Bit[4:3] Function Select Default= 0x01 =00 nDSR2 on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP75 0xDD General Purpose I/O bit 7.5 C Bit[4:3] Function Select Default= 0x01 =00 nRTS2 on VTR POR =01 GPI/O =10 Reserved =11 Reserved GP76 0xDE General Purpose I/O bit 7.6 C Bit[4:3] Function Select Default= 0x01 =00 nCTS2 on VTR POR =01 GPI/O =10 Reserved =11 Reserved 226 Table 105 (cont'd) - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE C GP77 0xDF General Purpose I/O bit 7.7 Bit[4:3] Function Select =00 nDTR2 Default= 0x01 =01 GPI/O on VTR POR =10 Reserved =11 Reserved 227 Definition for GP Registers Bit[0] In/Out: =1 Input, =0 Output Bit[1] Polarity: =1 Invert, =0 No Invert Bit[2] Int En 1: =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[4:3] Function Select =00 Original Function =01 Alternate Function 1 =10 Alternate Function 2 (or Reserved) =11 Alternate Function 3 (or Reserved) Bit[5] Reserved Bit[6] Int En 2 =1 Enable Combined IRQ 2 =0 Disable Combined IRQ 2 Bit[7] Open Collector: =1 Open Collector, =0 Push Pull Therefore, unless otherwise required, only Bit[4:3] are defined in the following table. Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP10 Default = 0x01 on VTR POR REG INDEX 0xE0 DEFINITION General Purpose I/0 bit 1.0 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func (If configured as input, the input signal is steered to the selected IRQ) =1 Select alternate function =0 Select basic I/O function Bit[7:4] Alt Fuct IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable STATE C 228 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP11 Default = 0x01 on VTR POR REG INDEX 0xE1 DEFINITION General Purpose I/0 bit 1.1 Bit[0] In/Out: =1 input, =0 Output Bit[1] Polarity: =1 invert, =0 No invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3-7] These bits are used for selection of the pin function as follows: Bit 7 6 5 4 3 Function Output Type IRQ Mapping 0 x x 0 0 GPIO Push Pull N/A 1 x x 0 0 GPIO Open Collector N/A 0 x x 1 0 IRQ13 Push Pull N/A 1 x x 1 0 IRQ13 Open Collector N/A 1 1 1 1 1 IRQIN Push Pull IRQ15 1 1 1 0 1 IRQIN Push Pull IRQ14 1 1 0 1 1 IRQIN Push Pull Reserved ..... 0 0 1 1 1 IRQIN Push Pull IRQ3 0 0 1 0 1 IRQIN Push Pull Reserved 0 0 0 1 1 IRQIN Push Pull IRQ1 0 0 0 0 1 IRQIN Push Pull Disable General Purpose I/0 bit 1.2 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func WDT output or IRRX input. =1 Select alternate function =0 Select basic I/O function (IRRX - if bit-6 of the IR Options Register is set) Bit[7:4] Reserved = 0000 STATE C GP12 Default = 0x01 on VTR POR 0xE2 C 229 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP13 Default = 0x01 on VTR POR REG INDEX 0xE3 DEFINITION General Purpose I/0 bit 1.3 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func Power LED or IRTX output =1 Select alternate function =0 Select basic I/O function (IRTX - if bit-6 of the IR Options Register is set) Bit[7:4] Reserved = 0000 General Purpose I/0 bit 1.4 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func: General Purpose Address Decode (Active Low) Decodes two address bytes =1 Select alternate function =0 Select basic I/O function Bit[7:4] Reserved = 0000 General Purpose I/0 bit 1.5 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func: Gen. Purpose Write Strobe (Active Low) =1 Select alternate function =0 Select basic I/O function Bit[7:4] Reserved = 0000 STATE C GP14 Default = 0x01 on VTR POR 0xE4 C GP15 Default = 0x01 on VTR POR 0xE5 C 230 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP16 Default = 0x01 on VTR POR REG INDEX 0xE6 DEFINITION General Purpose I/0 bit 1.6 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[4:3] Alt Func: Joystick (Active Low) =01 Joystick RD Strobe function =10 Joystick CS function =00 Select basic I/O function Bit[7:5] Reserved = 000 General Purpose I/0 bit 1.7 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Function: Joystick Write Strobe (Active Low) =1 Select alternate function =0 Select basic I/O function Bit[7:4] Reserved = 0000 General Purpose I/0 bit 2.0 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func: IDE2 buffer enable (Active Low) =1 Select alternate function =0 Select basic I/O function Bit[4] Alt function: 8042 P20, Typically used to generate a "Keyboard Reset" used by systems in order to switch from "protected mode" back to "real mode" =1 Select alternate function =0 Select basic I/O function Bit[7:5] Reserved = 000 Note: Bit[3] and Bit[4] should not both be set at the same time STATE C GP17 Default = 0x01 on VTR POR 0xE7 C GP20 Default = 0x01 on VTR POR 0xE8 C 231 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP21 Default = 0x01 on VTR POR REG INDEX 0xE9 DEFINITION General Purpose I/0 bit 2.1 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[4:3] Alt Func: =00 Select basic I/O function =01 Serial EEPROM Data In =10 AB_DATA Bit[6:5] Reserved = 0000 Bit[7] Open Collector: =1 Open Collector, =0 Push Pull General Purpose I/0 bit 2.2 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[4:3] Alt Func: =01 Serial EEPROM Data Out =00 Select basic I/O function =10 AB_CLK Bit[6:5] Reserved = 0000 Bit[7] Open Collector: =1 Open Collector, =0 Push Pull General Purpose I/0 bit 2.3 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[4:3] Function Select =00 GPIO =01 Serial EEPROM Clock =10 Either Edge Triggered Interrupt Input 2 Enable =11 Reserved Bit[7:5] Reserved = 0000 STATE C GP22 Default = 0x01 on VTR POR 0xEA C GP23 Default = 0x01 on VTR POR 0xEB C 232 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP24 Default = 0x01 on VTR POR REG INDEX 0xEC DEFINITION General Purpose I/0 bit 2.4 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[4:3] Function Select =00 GPIO =01 Serial EEPROM Enable =10 Either Edge Triggered Interrupt Input 3 Enable =11 Reserved Bit[7:5] Reserved = 000 General Purpose I/0 bit 2.5 Bit[0] In/Out =1 Input, =0 Output Bit[1] Polarity =1 Invert, =0 No Invert Bit[2] Int En =1 Enable Combined IRQ =0 Disable Combined IRQ Bit[3] Alt Func: GATEA20 =1 Select alternate function =0 Select basic I/O function Bit[7:4] : Reserved = 0000 Reserved General Purpose I/O Combined Interrupt 2 Bit[2:0] Reserved, = 000 Bit[3] GP IRQ Filter Select 0= Debounce Filter Bypassed 1= Debounce Filter Enabled Bit[7:4] Combined IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable STATE C GP25 Default = 0x01 on VTR POR 0xED C 0xEE GP_INT2 Default = 0x00 on VTR POR 0xEF C 233 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME GP_INT1 Default = 0x00 on VTR POR REG INDEX 0xF0 DEFINITION General Purpose I/O Combined Interrupt 1 Bit[2:0] Reserved, = 000 Bit[3] GP IRQ Filter Select 0= Debounce Filter Bypassed 1= Debounce Filter Enabled Bit[7:4] Combined IRQ mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable General Purpose Read/Write Enable Bit[0] =1 enable GP Address Decoder =0 disable GPA Address Decoder. Bit[1] =1 enable GPW, =0 disable GPW Bit[6:2] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds Note: If the logical device's activate bit is not set then bits 0 and 1 have no effect. WDT_VAL Default = 0x00 on VCC POR or Reset_Drv 0xF2 Watch-dog Timer Timeout Value Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of Reg 0xF1, Logical Device 8. 0x00 Timeout disabled 0x01 Timeout = 1 minute (second) ......... 0xFF Timeout = 255 minutes (seconds) C STATE C GPA_GPW_EN Default = 0x00 on VCC POR or Reset_Drv 0xF1 C 234 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME WDT_CFG Default = 0x00 on Vcc POR or Reset_Drv REG INDEX 0xF3 DEFINITION Watchdog Timer Configuration Bit[0] Joy-stick Enable =1 WDT is reset upon an I/O read or write of the Game Port =0 WDT is not affected by I/O reads or writes to the Game Port. Bit[1] Keyboard Enable =1 WDT is reset upon a keyboard interrupt. =0 WDT is not affected by keyboard interrupts. Bit[2] Mouse Enable =1 WDT is reset upon a mouse interrupt =0 WDT is not affected by mouse interrupts. Bit[3] PWRLED Timeout enable =1 Enables the Power LED to toggle at a 1Hz rate with 50 percent duty cycle while the Watchdog Status bit is set. =0 Disables the Power LED toggle during Watch-dog timeout status. Bit[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = Invalid 0001 = IRQ1 0000 = Disable Watchdog Timer Control Bit[0] Watch-dog Status Bit, R/W =1 WD timeout occured =0 WD timer counting Bit[1] Power LED Toggle Enable, R/W =1 Toggle Power LED at 1Hz rate with 50 percent duty cycle. (1/2 sec. on, 1/2 sec. off) =0 Disable Power LED Toggle Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is self-clearing Bit[3] P20 Force Timeout Enable, R/W = 1 Allows rising edge of P20, from the keyboard controller, to force the WD timeout event. A WD timeout event may still be forced by setting the Force Timeout Bit, bit 2. = 0 P20 activity does not generate the WD timeout event. STATE C WDT_CTRL Default = 0x00 Cleared by VTR POR 0xF4 C 235 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION The P20 signal will remain high for a minimum of 1us and can remain high indefinitely. Therefore, when P20 forced timeouts are enabled, a selfclearing edge-detect circuit is used to generate a signal which is ORed with the signal generated by the Force Timeout Bit. Bit[4] Reserved. Set to 0 Bit[5] Stop_Cnt: This is used to terminate Delay 2 (Note 1) without generating a power own. This is used if the software determines that the power down should be aborted. When read, this bit indicates the following: Stop_Cnt = 0; Counter running Stop_Cnt = 1; Counter Stopped. Note: The write is self clearing. Bit[6] Restart_Cnt: This is used to restart Delay 2 (Note 1) from the button input to the generation of the power down. When restarted, the count will start over and delay the power down for the time that Delay 2 is set for (Default=500msec). The software can continue to do this indefinately with out allowing a powerdown. This bit is self clearing. 1=Restart; Automatically cleared. Bit[7] SPOFF: This is used to force a software power down. This bit is self clearing. Note 1: This delay is programmable via the Delay 2 Time Set Register at Logical Device 8, 0xB8. GP1 Default = 0x00 on VCC POR or Reset_Drv GP2 Default = 0x00 on VCC POR or Reset_Drv GP4 Default = 0x00 on VCC POR or Reset_Drv 0xF6 Refer to Table 49 for Bit Definitions. STATE 0xF7 Refer to Table 49 for Bit Definitions. 0xF8 Refer to Table 49 for Bit Definitions. 236 Table 106 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX DEFINITION STATE 0xF9 Refer to Table 49 for Bit Definitions. GP5 Default = 0x00 on VCC POR or Reset_Drv 0xFA Refer to Table 49 for Bit Definitions. GP6 Default = 0x00 on VCC POR or Reset_Drv 0xFB Refer to Table 49 for Bit Definitions. GP7 Default = 0x00 on VCC POR or Reset_Drv Note: Registers GP1-2, WDT_CTRL, GP4-7, Soft Power and SMI Enable and Status Registers are also available at index 01-0F when not in configuration mode. See Table 49. Table 107 - Access Bus, Logical Device 9 [Logical Device Number = 0x09] NAME REG INDEX 0xF0 0xFF DEFINITION Reserved - read as "0" STATE Table 108 - ACPI, Logical Device A [Logical Device Number=0x0A] NAME REG INDEX DEFINITION 0xF0 0xFF Reserved - read as "0" STATE 237 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0oC to +70oC Storage Temperature Range..........................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) .................................................................... +325oC Positive Voltage on any pin, with respect to Ground ................................................................Vcc+0.3V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V Maximum Vcc ................................................................................................................................. +7V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0C - 70C, Vcc = +5 V 10%) PARAMETER SYMBOL MIN TYP MAX UNITS I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level ICLK2 Input Buffer Input Level 500 mV VP-P VILCK VIHCK 2.2 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels COMMENTS 238 PARAMETER Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage VBAT IBAT Standby Current Input Leakage SYMBOL MIN TYP MAX UNITS COMMENTS IIL IIH -10 -10 2.4 3.0 1.0 100 +10 +10 4.0 2.0 A A V A nA VIN = 0 VIN = VCC VCC=VSS=0 VCC=5V, VBAT=3V O4 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time O24 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V A IOL = 24 mA IOH = -12 mA VIN = 0 to VCC (Note 1) VOL VOH IOL TRT TFL 2.4 -10 5 5 +10 0.4 V V A ns ns IOL = 8 mA IOH = -8 mA VIN = 0 to VCC (Note 1) VOL VOH IOL 2.4 -10 +10 0.4 V V A IOL = 4 mA IOH = -2 mA VIN = 0 to VCC (Note 1) 239 PARAMETER O16SR Type Buffer Low Output Level High Output Level Output Leakage Rise Time Fall Time OD16P Type Buffer Low Output Level Output Leakage SYMBOL MIN TYP MAX UNITS COMMENTS VOL VOH IOL TRT TFL 2.4 -10 5 5 0.4 V V IOL = 16 mA IOH = -16 mA VIN = 0 to VCC (Note 1) +10 A ns ns VOL 0.4 V IOL OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level Output Leakage OCLK2 Type Buffer Low Output Level High Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR) VOL VOH IOL IIL VOL IOL VOL IOL -10 +10 A IOL = 16 mA IOH = 90 A (Note 2) VIN = 0 to VCC (Note 1) 0.4 +10 V A IOL = 24 mA VIN = 0 to VCC (Note 1) 0.4 +10 V A IOL = 48 mA VIN = 0 to VCC (Note 1) 0.4 3.5 -10 +10 10 V V A A IOL = 2 mA IOH = -2 mA VIN = 0 to VCC (Note 1) VCC = 0V VIN = 6V Max 240 PARAMETER Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) Suppy Current Active SYMBOL IIL MIN TYP MAX 10 UNITS A COMMENTS VCC = 0V VIN = 6V Max VCC = 0V VIN = 6V Max All outputs open. IIL ICCI 4.5 70 10 90 A mA Note 1: Note 2: All output leakages are measured with the current pins in high impedance. Output leakage is measured with the low driving output off, either for a high level output or a high impedance state. KBCLK, KBDATA, MCLK, MDATA contain 90A min pull-ups. CAPACITANCE TA = 25C; fc = 1 MHz; VCC = 5V PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN LIMITS TYP MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground 241 POWER SUPPLY OPERATIONAL MODES Standard Operational Modes Table 109 - Standard Operational Modes For The Power Supplies. MODE VBAT VTR VCC RTC Only (1) 3.3V 0 0 Standby (2) (3) 3.3V 5V @ 2mA Max 0 Full Power (2) 3.3V 5V @ 2mA Max 5V Note 1: RTC power supplied by Vbat Note 2: RTC power supplied by VTR Note 3: In standby mode, the following are operational: RTC, RTC Alarm 2, power control (wakeup) logic (button input and power on) and soft power management logic. When VCC goes away, certain registers will be powered by VTR. Similarly, when VTR goes away, certain registers will be powered by Vbat. These registers are discussed in the Soft Power Management and RTC Section. Power Supply Non-Standard Modes Table 110 - Non-Standard Operational Modes For The Power Supplies. NON-STANDARD MODE VBAT VTR VCC NS1 0 5V @ 2mA Max 0 NS2 0 5V @ 2mA Max 5V NS3 0 0 5V NS4 3.3V 0 5V 242 TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used. CAPACITANCE TOTAL (pF) 240 240 120 120 50 50 50 50 50 240 240 240 240 240 240 240 240 100 100 100 100 100 100 100 240 240 240 240 240 240 240 240 240 240 240 240 240 NAME SD[0:7] IOCHRDY IRQ[1,3:12,14,15] DRQ[0:3] HCLK 16CLK CLK01 CLK02 CLK03 nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 nIDE1_OE nHDCS0 nHDCS1 nIOROP nIOWOP nHDCS2 nHDCS3 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK 243 NAME MDAT MCLK nPowerOn Button_In GP1[0:7], GP2[0:5] RD[0:7] CAPACITANCE TOTAL (pF) 240 240 100 100 100 100 244 B u tto n _ I n tF tR FIGURE 15A - BUTTON INPUT TIMING NAME tR, tF DESCRIPTION Button_In Rise/Fall Time MIN TYP MAX 0.5 UNITS s B u tto n _ In t1 R e le a s e n P o w e rO n t2 B la n k in g P e rio d t3 Vcc FIGURE 15B - BUTTON OVERRIDE TIMING NAME t1 t2 t3 DESCRIPTION Button_In Hold Time For Override Event Button _In Low To nPowerOn Tristate and Vcc Low and Start of Blanking Period Blanking Period After Release of Button_In MIN 4 TYP 4 4 MAX UNITS s s s 245 t3 SAx t4 SD<7:0> nIOW t1 t2 t5 FIGURE 16 - IOW TIMING FOR PORT 92 IOW TIMING NAME t1 t2 t3 t4 t5 DESCRIPTION SAx Valid to nIOW Asserted SDATA Valid to nIOW Asserted nIOW Asserted to SAx Invalid nIOW Deasserted to DATA Invalid nIOW Deasserted to nIOW or nIOR Asserted MIN 40 0 10 0 100 TYP MAX UNITS ns ns ns ns ns 246 t1 V cc t2 t3 A ll H o s t A ccesses FIGURE 17 - POWER-UP TIMING NAME t1 t2 t3 DESCRIPTION Vcc Slew from 4.5V to 0V Vcc Slew from 0V to 4.5V All Host Accesses After Powerup (Note 1) MIN 300 100 125 500 TYP MAX UNITS s s s Note 1: Internal write-protection period after Vcc passes 4.5 volts on power-up 247 t10 AEN t3 SA[x], nCS t2 t1 nIOW t4 t11 t5 SD[x] DATA VALID t6 GP I/O t7 FINTR t8 PINTR t9 IBF FIGURE 18 - ISA WRITE NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 DESCRIPTION SA[x], nCS and AEN Valid to nIOW Asserted nIOW Asserted to nIOW Deasserted nIOW Asserted to SA[x], nCS Invalid SD[x] Valid to nIOW Deasserted SD[x] Hold from nIOW Deasserted nIOW Deasserted to nIOW Asserted nIOW Deasserted to FINTR Deasserted (Note 2) nIOW Deasserted to PINTER Deasserted (Note 3) IBF (Internal Signal) Asserted from nIOW Deasserted nIOW Deasserted to AEN Invalid nIOW Deasserted to GPI/O Out Valid 10 100 25 55 260 40 MIN 10 80 10 45 0 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns Note 1: If ACCESS.bus is used at 12 MHz, use 100 ns. Note 2: FINTR refers to the IRQ used by the floppy disk. Note 3: PINTR refers to the IRQ used by the parallel port 248 t13 AEN t3 SA[x], nCS t1 t7 nIOR t4 SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY t10 FINTER t9 PINTER t11 PCOBF t12 AUXOBF1 t8 nIOR/nIOW DATA VALID t5 t2 t6 FIGURE 19 - ISA READ SEE TIMING PARAMETERS ON NEXT PAGE 249 NAME t1 t2 t3 t4 t5 t6 t8 t8 t7 t9 t10 t11 t12 t13 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: ISA READ TIMING DESCRIPTION SA[x], nCS and AEN valid to nIOR asserted nIOR Asserted to nIOR Deasserted nIORAsserted to SA[x], nCS Invalid nIOR Asserted to Data Valid Data Hold/float from nIOR Deasserted nIOR Deasserted nIOR Aserted after nIOW Deasserted nIOR/nIOR, nIOW/nIOW Transfers from/to ECP FIFO Parallel Port Setup to nIOR Asserted nIOR Asserted to PINTER Deasserted nIOR Deasserted to FINTER Deasserted nIOR Deasserted to PCOBF Deasserted (Notes 4,6) nIOR Deasserted to AUXOBF1 Deasserted (Notes 5,6) nIOW Deasserted to AEN Invalid MIN 10 50 10 TYP MAX UNITS ns ns ns 50 10 25 80 150 20 55 260 80 80 10 25 ns ns ns ns ns ns ns ns ns ns ns If ACCESS.bus is used at a clock rate below 24 MHz, use 100 ns. FINTR refers to the IRQ used by the floppy disk. PINTR refers to the IRQ used by the parallel port. PCOBF is used for the Keyboard IRQ. AUXOBF1 is used for the Mouse IRQ. Applies only if deassertion is performed in hardware. 250 t2 PCOBF t1 AUXOBF1 nWRT t3 IBF nRD FIGURE 20 - INTERNAL 8042 CPU TIMING NAME t1 t2 t3 DESCRIPTION nWRT Deasserted to AUXOBF1 Asserted (Notes 1,2) nWRT Deasserted to PCOBF Asserted (Notes 1,3) nRD Dasserted to IBF Deasserted (Note 1) MIN TYP MAX 40 40 40 UNITS ns ns ns Note 1: IBF, nWRT and nRD are internal signals. Note 2: PCOBF is used for the Keyboard IRQ. Note 3: AUXOBF1 is used for the Mouse IRQ. 251 t1 t2 X1K FIGURE 21A - INPUT CLOCK TIMING NAME t1 t2 t1 t2 DESCRIPTION Clock Cycle Time for 14.318 MHZ Clock High Time/Low Time for 14.318 MHz Clock Cycle Time for 32 KHz Clock High Time/Low Time for 32 KHz Clock Rise Time/Fall Time (not shown) MIN TYP 70 35 31.25 16.53 5 MAX UNITS ns ns s s ns t2 t4 RESET FIGURE 21B - RESET TIMING NAME t4 DESCRIPTION RESET Width (Note 1) MIN 1.5 TYP MAX UNITS s Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while the clock is running and stable. 252 IDEx_IRQ t1 IRQx FIGURE 22 - IRQ TIMING t2 NAME t1 DESCRIPTION IDE_IRQ Low-High Edge to IRQ Low-High Edge Propagation Delay. Edge High Type Interrupt Selected. IDE_IRQ High-Low Edge to IRQ High-Low Edge Propagation Delay. Edge High Type Interrupt Selected. IDE IRQ input and pass-through IRQ timing MIN TYP MAX 30 UNITS ns t2 30 ns Note: Definition: IDE_ IRQ is the Interrupt request input from an IDE Hard Drive which is defined as a low to high edge type interrupt held high until the interrupt is serviced. 253 nIOR t2 t2 nIOROP nIOW nIOW O P t3 t3 FIGURE 23 - nIOROP, nIOWOP TIMING NAME t2 t3 DESCRIPTION nIOR in to nIOROP Output nIOW in to nIOWOP Output MIN TYP MAX 25 25 UNITS ns ns 254 nROMCS nROMOE t2 t1 RD[x] Note 1 t5 S D [x] FIGURE 24 - ROM INTERFACE TIMING Note 1: RD[x] driven by FDC37C93x, SD[x] driven by system Note 2: RD[x] driven by ROM, SD[x] driven by FDC37C93xAPM NAME t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION SD[x] Valid to RD[x] Valid nROMCS Active to RD[X] Driven nROMCS Inactive to RD[X] Float RD[x] Valid to SD[x] Valid nROMCS Active to SD[X] Driven nROMCS Inactive to SD[X] Float nROMOE Active to RD[x] Float nROMOE Inactive to RD[x] Driven MIN TYP MAX 25 25 25 25 25 25 25 25 UNITS ns ns ns ns ns ns ns ns t7 N o t e 2 t3 t2 t8 t3 t4 t6 Note 1: Outputs have a 50 pf load. 255 t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK t12 t14 t11 t6 t5 nIOR or nIOW t7 DATA (DO-D7) t13 TC DATA VALID t8 t4 t10 t9 FIGURE 25A - DMA TIMING (SINGLE TRANSFER MODE) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive 40 10 10 5 10 60 40 10 100 60 150 0 0 100 MIN 0 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 256 t15 AEN t16 t3 t2 FDRQ, PDRQ t1 nDACK t12 t14 t11 t6 nIOR or nIOW t5 t8 t4 t7 DATA (DO-D7) DATA VALID t13 TC t10 t9 DATA VALID FIGURE 25B - DMA TIMING (BURST TRANSFER MODE) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 DESCRIPTION nDACK Delay Time from FDRQ High DRQ Reset Delay from nIOR or nIOW FDRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from FDRQ High nIOW Delay from FDRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High TC Pulse Width AEN Set Up to nIOR/nIOW AEN Hold from nDACK TC Active to PDRQ Inactive 40 10 10 5 10 60 40 10 100 60 150 0 0 100 MIN 0 100 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 257 t3 nDIR t4 t1 nSTEP t2 t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW t9 nDS0-1, MTR0-1 t9 FIGURE 26 - DISK DRIVE TIMING (AT MODE ONLY) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTRO-1 from End of nIOW MIN TYP 4 24 96 132 20 2 40 .5 25 MAX UNITS X* X* X* X* X* X* ns Y* ns *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kbps MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kbps WCLK = 1 MHz) 258 nIOW t1 nRTSx, nDTRx t5 IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW t4 t6 t3 IRQx nIOR nRIx FIGURE 27 - SERIAL PORT TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION nRTSx, nDTRx Delay from nIOW IRQx Active Delay from nCTSx, nDSRx, nDCDx IRQx Inactive Delay from nIOR (Leading Edge) IRQx Inactive Delay from nIOW (Trailing Edge) IRQx Inactive Delay from nIOW IRQx Active Delay from nRIx MIN TYP MAX 200 100 120 125 UNITS ns ns ns ns ns ns 10 100 100 259 nAEN A0-A9 t2 t1 nIDEENLO, nIDEENHI, nHDCSx, nGAMECS t3 FIGURE 28 - IDE INTERFACE TIMING NAME t1 t2 t3 DESCRIPTION nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from nAEN nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from A0 - A9 nIDEENLO Delay from nIDEENHI, AEN MIN TYP MAX 40 40 40 UNITS ns ns ns 260 PD0- PD7 t6 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK t2 t1 nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) t4 t3 t5 t2 PINTR t3 FIGURE 29 - PARALLEL PORT TIMING NAME t1 t2 t3 t4 t5 t6 Note: DESCRIPTION PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW PINTR Delay from nACK, nFAULT PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK nERROR Active to PINTR Active PD0 - PD7 Delay from IOW Active PINTR refers to the IRQ used by the parallel port. MIN TYP MAX 100 60 UNITS ns ns ns ns ns ns 200 300 105 105 100 261 t18 A0-A10 t9 SD<7:0> nIOW IOCHRDY t13 t22 t20 t1 PD<7:0> t14 t16 t3 t4 t17 t8 t10 t11 t12 t19 nWRITE t2 t5 nDATAST nADDRSTB t6 nWAIT t21 PDIR t15 t7 FIGURE 30A - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 262 FIGURE 30B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 DESCRIPTION nIOW Asserted to PDATA Valid nWAIT Asserted to nWRITE Change (Note 1) nWRITE to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) Time Out Command Deasserted to nWAIT Asserted SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted nWAIT Asserted to Command Asserted (Note 1) Command Asserted to nWAIT Deasserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Asserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to PDIR Low PDIR Low to nWRITE Asserted MIN 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60 0 0 185 70 210 10 24 160 12 TYP MAX 50 185 35 190 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns WAIT is Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. considered to have settled after it does not transition for a minimum of 50 nsec. 263 t20 A0-A10 IOR t19 t13 SD<7:0> t8 t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 DATASTB ADDRSTB t15 t7 nWAIT t6 t14 t3 t5 PData bus driven by peripheral t11 t12 t18 t10 t22 IOCHRDY t27 t17 t4 t16 FIGURE 31A - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 264 FIGURE 31B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Note 1: Note 2: Note 3: DESCRIPTION PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted (Note 1) Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Asserted to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted (Note 2) nWAIT Deasserted to IOCHRDY Deasserted (Note 1) IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven (Note 1) nWAIT Deasserted to nWRITE Modified (Notes 1,2) SDATA Valid to IOCHRDY Deasserted (Note 3) Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDIR Set (Note 1) PDATA Hi-Z to PDIR Set nWAIT Asserted to PDATA Hi-Z (Note 1) PDIR Set to Command nWAIT Deasserted to PDIR Low (Note 1) nWRITE Deasserted to Command MIN 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 0 60 0 60 1 180 20 180 185 10 185 40 75 195 12 190 190 85 160 24 TYP MAX 30 50 180 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high. 85 is true only if t7 = 0. 265 t18 A0-A10 t9 SD<7:0> t17 t8 t6 t12 t10 t20 t19 nIOW IOCHRDY t13 nWRITE t1 PD<7:0> t11 t2 t5 t16 t3 nDATAST nADDRSTB t4 t21 nWAIT PDIR FIGURE 32A - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 266 FIGURE 32B - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 DESCRIPTION nIOW Asserted to PDATA Valid Command Deasserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted (Note 2) Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted 0 10 0 10 40 10 100 45 50 35 50 10 10 0 0 24 40 12 MIN 0 0 5 TYP MAX 50 40 35 50 UNITS ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. Note 2: The number is only valid if nWAIT is active when IOW goes active. 267 t20 A0-A10 t15 t19 nIOR t13 SD<7:0> t8 t3 IOCHRDY t10 t11 t22 t12 nWRITE t5 PD<7:0> t23 nDATASTB nADDRSTB t2 t4 t21 nWAIT PDIR FIGURE 33A - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE 268 FIGURE 33B - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 Note: DESCRIPTION nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time) PDATA Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted 10 40 10 0 40 55 0 0 40 40 12 0 0 0 24 50 MIN TYP MAX 50 40 UNITS ns ns ns ns ns ns ns ns ns s ns ns ns ns ns WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. 269 ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 34. ECP Parallel Port Timing Reverse-Idle Phase The timing is designed to allow operation at approximately 2.0 Mbps over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 36. Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 35. The timing is designed to provide three cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). 270 open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. t6 t3 PDATA t1 t2 t5 nSTROBE t4 BUSY FIGURE 34 - PARALLEL PORT FIFO TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) 680 80 MIN 600 600 450 500 TYP MAX UNITS ns ns ns ns ns ns Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. 271 t3 nAUTOFD t4 PDATA<7:0> t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8 FIGURE 35 - ECP PARALLEL PORT FORWARD TIMING NAME t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION nAUTOFD Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed (Notes 1,2) BUSY Deasserted to PDATA Changed (Notes 1,2) nSTROBE Deasserted to Busy Asserted nSTROBE Deasserted to Busy Deasserted BUSY Deasserted to nSTROBE Asserted (Notes 1,2) BUSY Asserted to nSTROBE Deasserted (Note 2) MIN 0 0 80 80 0 0 80 80 TYP MAX 60 60 180 180 UNITS ns ns ns ns ns ns 200 180 ns ns Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out. Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 272 t2 PDATA<7:0> t1 t5 nACK t4 nAUTOFD FIGURE 36 - ECP PARALLEL PORT REVERSE TIMING NAME t1 t2 t3 t4 t5 t6 DESCRIPTION PDATA Valid to nACK Asserted nAUTOFD Deasserted to PDATA Changed nACK Asserted to nAUTOFD Deasserted (Notes 1,2) nACK Deasserted to nAUTOFD Asserted (Note 2) nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted MIN 0 0 80 80 0 0 200 200 TYP MAX UNITS ns ns ns ns ns ns t6 t3 t4 Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nAUTOFD low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. 273 AB_DATA tBUF tLOW tR tF tHD;STA AB_CLK tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO FIGURE 37 - ACCESS.BUS TIMING SYMBOL fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tR tF tSU;DAT tHD;DAT tSU;STO Bus Free Time START Condition Setup Time START Condition Hold Time SCL LOW Time SCL HIGH Time SCL and SDA Rise Time SCL and SDA Fall Time Data Set-Up Time Data Hold Time STOP Condition Setup Time 250 0 4.0 PARAMETER SCL Clock Frequency 4.7 4.7 4.0 4.7 4.0 1.0 0.3 MIN. TYP. MAX. 100 UNIT KHz s s s s s s s s s s 274 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRRX nIRRX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Width at 57.6kbaud Pulse Width at 38.4kbaud Pulse Width at 19.2kbaud Pulse Width at 9.6kbaud Pulse Width at 4.8kbaud Pulse Width at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.4 1.4 1.4 1.4 1.4 1.4 1.4 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s Note1: Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41s. Note 2: IRRX: L5, CRF1 Bit 0: 1 = RCV active low nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default) Note 3: This polarity assumes that the GPIO has not been programmed for inverted. FIGURE 38 - IrDA RECEIVE TIMING 275 DATA 0 t2 t1 1 0 1 0 0 1 1 0 1 1 t2 t1 IRTX n IRTX Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse W idth at 115kbaud Pulse W idth at 57.6kbaud Pulse W idth at 38.4kbaud Pulse W idth at 19.2kbaud Pulse W idth at 9.6kbaud Pulse W idth at 4.8kbaud Pulse W idth at 2.4kbaud Bit Time at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Time at 9.6kbaud Bit Time at 4.8kbaud Bit Time at 2.4kbaud min 1.41 1.41 1.41 1.41 1.41 1.41 1.41 typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default) nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high 3. This polarity assumes that the GPIO has not been programmed for inverted. FIGURE 39 - IrDA TRANSMIT TIMING 276 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRRX n IRRX t3 MIRRX t4 t5 nMIRRX t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off" min typ max units s s 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 s s s s Note 1: IRRX: L5, CRF1 Bit 0: 1 = RCV active low nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default) MIRRX, nMIRRX are the modulated outputs Note 2: This polarity assumes that the GPIO has not been programmed for inverted. FIGURE 40 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING 277 DATA 0 t1 1 t2 0 1 0 0 1 1 0 1 1 IRTX nIRTX t3 MIRTX t5 nMIRTX t4 t6 Parameter t1 t2 t3 t4 t5 t6 Modulated Output Bit Time Off Bit Time Modulated Output "On" Modulated Output "Off" Modulated Output "On" Modulated Output "Off" min typ max units s s 0.8 0.8 0.8 0.8 1 1 1 1 1.2 1.2 1.2 1.2 s s s s Note 1: IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default)nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high MIRTX, nMIRTX are the modulated outputs This polarity assumes that the GPIO has not been programmed for inverted. Note 2: FIGURE 41 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING 278 D DETAIL "A" R1 R2 121 0 L 5 L1 120 D1 3 81 80 E E1 2 7 D1/4 E1/4 W e 41 40 160 1 A H A2 T/T D E 4 1 -C- 0.10 0 A1 SEE DETAIL "A" M IN A A1 A2 D D1 E3 E1 H L L1 e 0 W R1 R2 TD TE 0 0.20 0.05 3.10 30.95 27.90 30.95 27.90 0.10 0.65 NOM MAX 4.07 0.5 3.67 Notes: 1) 2) 3) Coplanarity is 0.100 mm maximum Tolerance on the position of the leads is 0.120 mm maximum Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm Dimensions T D and TE are important for testing by robotic handler Dimensions for foot length L w hen measured at the centerline of the leads are given at the table Dimension for foot length L w hen measured at the gauge plane 0.25 mm above the seating plane is 0.78 - 1.03 mm Controlling dimension: millimeter Details of pin 1 identifier are optional but must be located w ithin the zone indicated 31.20 28.00 31.20 28.00 0.80 1.60 0.65BSC 31.45 28.10 31.45 28.10 0.200 0.95 4) 5) 7 0.40 0.20 0.30 30.45 30.45 6) 7) FIGURE 42 - 160 PIN QFP PACKAGE OUTLINES 279 1999(c) STANDARD MICROSYSTEMS CORP. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. SMSC reserves the right to make changes at any time in order to improve design and supply the best product possible. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. FDC37C93xAPM Rev. 11/02/99 |
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